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Cleanup in script and trace workaround file

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This commit is contained in:
Mahesh Asolkar
2025-08-24 21:02:01 -07:00
parent 5451131e1a
commit 4efbada1d8
2 changed files with 135 additions and 119 deletions
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32
scripts/gen_axi_intf.pl
View File

@@ -2,14 +2,27 @@
use strict;
use warnings;
use Data::Dumper;
use Getopt::Long;
my $app = {};
$app->{'cfg'}->{'gen_intf'} = 0;
$app->{'cfg'}->{'gen_trace_wa'} = 0;
GetOptions("gen_intf" => \$app->{'cfg'}->{'gen_intf'},
"gen_trace_wa" => \$app->{'cfg'}->{'gen_trace_wa'});
get_axi_intf_data($app);
augment_intf_data($app);
#print Dumper($app->{'intf_data'}); # Debugging output
gen_intf($app);
if ($app->{'cfg'}->{'gen_intf'}) {
gen_intf($app);
}
if ($app->{'cfg'}->{'gen_trace_wa'}) {
show_trace_interface_driver($app);
}
# -----------------
# Subroutines
@@ -38,8 +51,6 @@ sub gen_intf {
show_modport($app, 'Subordinate');
print "endinterface // axi_intf\n";
show_trace_interface_driver($app);
}
# -----------------
@@ -94,10 +105,11 @@ sub show_interface {
sub show_trace_interface_driver {
my ($app) = @_;
print qq{
`ifdef VERI_TRACE_EN
print qq{`ifdef VERI_TRACE_EN
// --------------------------------------------------
// Work around Verilator's lack of support for virutal interface tracing
// Work around Verilator's lack of support for virutal interface tracing:
// Issue #5044: Wires driven through virtual interface traced improperly
// https://github.com/verilator/verilator/issues/5044
`AXI_INTF t_if (.ACLK(clk), .ARESETn(rst_n));
};
foreach my $section (@{$app->{'intf_data'}->{'sections'}}) {
@@ -105,12 +117,16 @@ sub show_trace_interface_driver {
# Display signals
foreach my $signal (@{$section->{'signals'}}) {
my $line = "";
if ($signal->{'s'} eq 'External') {
printf " // External signal: %-$app->{'intf_data'}->{'info'}->{'sig_width'}s // $signal->{'d'} [$signal->{'s'}]\n",
$line = sprintf " // External signal: %-$app->{'intf_data'}->{'info'}->{'sig_width'}s // $signal->{'d'} [$signal->{'s'}]",
"$signal->{'n'};";
} else {
printf " always @(a_if.$signal->{'n'}) t_if.$signal->{'n'} <= a_if.$signal->{'n'};\n";
$line = sprintf " always @(a_if.%-$app->{'intf_data'}->{'info'}->{'sig_width'}s t_if.%-$app->{'intf_data'}->{'info'}->{'sig_width'}s <= a_if.%-$app->{'intf_data'}->{'info'}->{'sig_width'}s",
"$signal->{'n'})", $signal->{'n'}, "$signal->{'n'};";
}
$line =~ s/\s+$//;
print "$line\n";
}
}

6
tb/verilator_trace_workaround.svh
View File

@@ -1,8 +1,8 @@
// Issue #5044: Wires driven through virtual interface traced improperly
// https://github.com/verilator/verilator/issues/5044
`ifdef VERI_TRACE_EN
// --------------------------------------------------
// Work around Verilator's lack of support for virutal interface tracing
// Work around Verilator's lack of support for virutal interface tracing:
// Issue #5044: Wires driven through virtual interface traced improperly
// https://github.com/verilator/verilator/issues/5044
`AXI_INTF t_if (.ACLK(clk), .ARESETn(rst_n));
// A2.4.1 Clock and reset signals
// External signal: ACLK; // External Global clock signal [External]