Interface clean up. WA for verilator tracing

scripts/gen_axi_intf.pl

@@ -38,6 +38,8 @@ sub gen_intf {
     show_modport($app, 'Subordinate');
 
     print "endinterface // axi_intf\n";
+
+    show_trace_interface_driver($app);
 }
 
 # -----------------
@@ -88,6 +90,35 @@ sub show_interface {
     }
 }
 
+# -----------------
+sub show_trace_interface_driver {
+    my ($app) = @_;
+
+    print qq{
+`ifdef VERI_TRACE_EN
+    // --------------------------------------------------
+    // Work around Verilator's lack of support for virutal interface tracing
+    `AXI_INTF t_if (.ACLK(clk), .ARESETn(rst_n));
+};
+    foreach my $section (@{$app->{'intf_data'}->{'sections'}}) {
+        print "    // $section->{'name'}\n";
+
+        # Display signals
+        foreach my $signal (@{$section->{'signals'}}) {
+            if ($signal->{'s'} eq 'External') {
+                printf "    // External signal: %-$app->{'intf_data'}->{'info'}->{'sig_width'}s // $signal->{'d'} [$signal->{'s'}]\n",
+                    "$signal->{'n'};";
+            } else {
+                printf "    always @(a_if.$signal->{'n'}) t_if.$signal->{'n'} <= a_if.$signal->{'n'};\n";
+            }
+        }
+    }
+
+    print qq{
+`endif
+};
+}
+
 # -----------------
 sub show_modport{
     my ($app, $role) = @_;