Interface clean up. WA for verilator tracing

tb/tb_intf.sv

@@ -1,26 +1,30 @@
 // Testbench interface for UVM-based verification environment
 interface testbench_if (
-    input clk,
-    virtual axi_intf #(.ADDR_WIDTH(`ADDR_WIDTH),
-               .CEIL_DATA_WIDTH_DIV_128(`CEIL_DATA_WIDTH_DIV_128),
-               .CEIL_DATA_WIDTH_DIV_128_TMS_4(`CEIL_DATA_WIDTH_DIV_128_TMS_4),
-               .CEIL_DATA_WIDTH_DIV_64(`CEIL_DATA_WIDTH_DIV_64),
-               .DATA_WIDTH(`DATA_WIDTH),
-               .DATA_WIDTH_DIV_8(`DATA_WIDTH_DIV_8)) m_if,
-    virtual axi_intf #(.ADDR_WIDTH(`ADDR_WIDTH),
-               .CEIL_DATA_WIDTH_DIV_128(`CEIL_DATA_WIDTH_DIV_128),
-               .CEIL_DATA_WIDTH_DIV_128_TMS_4(`CEIL_DATA_WIDTH_DIV_128_TMS_4),
-               .CEIL_DATA_WIDTH_DIV_64(`CEIL_DATA_WIDTH_DIV_64),
-               .DATA_WIDTH(`DATA_WIDTH),
-               .DATA_WIDTH_DIV_8(`DATA_WIDTH_DIV_8)) s_if);
+    output clk,
+    output rst_n
+);
 
-    logic rst_n;
+    logic clk_w;
+    logic rst_n_w;
 
+    assign clk = clk_w;
+    assign rst_n = rst_n_w;
+
+    // --------------------------------------------------
+    // Clock generation
     initial begin
+        clk_w = 0; // Initialize clock to 0 at time 0
         forever begin
-            @(clk or rst_n);
-                $monitor("@%6t: %b %b ", $time,
-                    rst_n, clk);
+            #5ns clk_w = ~clk_w; // Toggle clock every 5 ns
         end
     end
+
+    // --------------------------------------------------
+    // Initial reset
+    initial begin
+        rst_n_w = 0;
+
+        repeat(20) @(posedge clk_w);
+        rst_n_w = 1; // Release reset after 20 clocks
+    end
 endinterface