From 90dbd81844a57396e86cc1a7b4d30962c755c1e4 Mon Sep 17 00:00:00 2001
From: Mahesh Asolkar <mahesh@mahesha.com>
Date: Sun, 28 Dec 2025 18:03:50 -0800
Subject: [PATCH] Miscellaneous makefile updates

---
 Makefile | 59 ++++++++++++++++++++++++++++++++++++++++----------------
 1 file changed, 42 insertions(+), 17 deletions(-)

diff --git a/Makefile b/Makefile
index 7584890..8db7d2d 100644
--- a/Makefile
+++ b/Makefile
@@ -3,12 +3,23 @@ LOG_REDIR = >&
 TIME=/usr/bin/time --format "Elapsed: %E, Memory: %M KB [Swaps %W]"
 
 # Makefile variables
-# NUM_PROCS=$(shell nproc --all)
-NUM_PROCS=6
+# Use as many threads as possible while keeping 2 for IO, browsing, etc.
+# USE_PROCS = $(( $(shell nproc --all) - 2 ))
+KEEP_PROCS=2
+TOTAL_PROCS=$(shell nproc --all)
+USE_PROCS=$(shell expr $(TOTAL_PROCS) - $(KEEP_PROCS))
 PROJ_BASE=$(shell pwd)
 
-# Make and run project
+# Verilator setup
+# VERILATOR_HOME=$(HOME)/git/verilator
+VERILATOR_HOME=/usr/share/verilator
+
+# UVM setup
 UVM_HOME=$(HOME)/git/uvm-verilator
+# UVM_HOME=$(HOME)/git/ca_uvm-verilator
+# UVM_HOME=$(HOME)/git/1800.2-2017-1.0
+
+# Make and run project
 PROJ=axi
 
 SV_OUT=obj_dir/Vuvm_pkg__verFiles.dat
@@ -22,7 +33,7 @@ SIM_LOG=$(PROJ)_sim.log
 SV_FILES=$(shell ls common/*.sv src/axi/*.sv tb/*.sv)
 SV_SRC=$(UVM_HOME)/src/uvm_pkg.sv common/common_pkg.sv src/axi/axi_types.sv src/axi/axi_pkg.sv tb/tb_pkg.sv
 DPI_SRC=$(UVM_HOME)/src/dpi/uvm_dpi.cc
-DPI_INC=-I/usr/share/verilator/include
+DPI_INC=-I$(VERILATOR_HOME)/include
 SV_DEPS=$(SV_FILES)
 
 CPP_SRC=sim_$(PROJ).cpp
@@ -41,7 +52,7 @@ DISABLED_WARNINGS=-Wno-WIDTHTRUNC  -Wno-WIDTHEXPAND \
 
 BUILD_ARGS=-I$(UVM_HOME)/src -I. \
         -o $(PROJ).sim \
-        -j $(NUM_PROCS) \
+        -j $(USE_PROCS) \
         --error-limit 10 \
         --timing $(TIMESCALE) \
         --trace \
@@ -79,10 +90,10 @@ $(PROJ_BASE)/logs:
 	@if [ ! -d $(PROJ_BASE)/logs ]; then mkdir -p $(PROJ_BASE)/logs; fi
 
 $(SV_OUT): $(PROJ_BASE)/logs $(SV_DEPS)
-	$(info #------------)
-	$(info # Building SV)
-	$(info #------------)
-	@verilator --cc $(BUILD_ARGS)
+	$(info #------------------------)
+	$(info # Building SV ($(USE_PROCS) threads))
+	$(info #------------------------)
+	@$(VERILATOR_HOME)/bin/verilator --cc $(BUILD_ARGS)
 
 #
 # C code build to generate testbench executable
@@ -90,10 +101,10 @@ $(SV_OUT): $(PROJ_BASE)/logs $(SV_DEPS)
 build_cpp: build_sv $(CPP_OUT)
 
 $(CPP_OUT): $(SV_OUT)
-	$(info #-------------)
-	$(info # Building CPP)
-	$(info #-------------)
-	@verilator --binary $(BUILD_ARGS)
+	$(info #-------------------------)
+	$(info # Building CPP ($(USE_PROCS) threads))
+	$(info #-------------------------)
+	@$(VERILATOR_HOME)/bin/verilator --binary $(BUILD_ARGS)
 
 #
 # Run just lint to detect syntax errors during development
@@ -102,20 +113,34 @@ lint:
 	$(info #--------)
 	$(info # Linting)
 	$(info #--------)
-	@verilator --lint-only $(BUILD_ARGS)
+	@$(VERILATOR_HOME)/bin/verilator --lint-only $(BUILD_ARGS)
 
 #
 # Run test. Use TEST_NAME=<test name> on make line to pick the test
 #
-run: $(CPP_OUT)
+#run: $(CPP_OUT)
+run:
 	$(info #---------------------)
 	$(info # Running $(TEST_NAME))
 	$(info #---------------------)
 	@if [ ! -d runs/$(TEST_NAME) ]; then mkdir -p runs/$(TEST_NAME); fi
-	@cd runs/$(TEST_NAME) && \
-        $(PROJ_BASE)/obj_dir/$(PROJ).sim +verilator+seed+2 +UVM_TESTNAME=$(TEST_NAME) +UVM_CONFIG_DB_TRACE |& tee $(SIM_LOG)
+	cd runs/$(TEST_NAME) && \
+        $(PROJ_BASE)/obj_dir/$(PROJ).sim +verilator+seed+2 \
+            +UVM_TESTNAME=$(TEST_NAME) \
+            +UVM_VERBOSITY=UVM_MEDIUM \
+            +uvm_set_verbosity=uvm_test_top.*,_ALL_,UVM_MEDIUM,run \
+            +UVM_CONFIG_DB_TRACE |& tee $(SIM_LOG)
 	notify-send "[$(PROJ)] Test run done"
 
+build_and_run: $(CPP_OUT) run
+	$(info Build and Run done)
+
+info:
+	$(info #----------------------)
+	$(info # Procs: $(TOTAL_PROCS))
+	$(info # Keep: $(KEEP_PROCS))
+	$(info # Threads: $(USE_PROCS))
+	$(info #----------------------)
 #
 # Remove generated files
 # - This will not remove 'runs' directory that contains simulation run logs