// Testbench interface for UVM-based verification environment
interface testbench_if (
    output clk,
    output rst_n
);

    logic clk_w;
    logic rst_n_w;

    assign clk = clk_w;
    assign rst_n = rst_n_w;

    // --------------------------------------------------
    // Clock generation
    initial begin
        clk_w = 0; // Initialize clock to 0 at time 0
        forever begin
            #5ns clk_w = ~clk_w; // Toggle clock every 5 ns
        end
    end

    // --------------------------------------------------
    // Initial reset
    initial begin
        rst_n_w = 0;

        repeat(20) @(posedge clk_w);
        rst_n_w = 1; // Release reset after 20 clocks
    end
endinterface