// Testbench top module for UVM-based verification environment
import uvm_pkg::*;

module tb_top (input logic sys_clk);
    logic clk;
    logic rst_n;

    // Testbench interface to controll clocks, reset, etc.
    testbench_if tb_if(.clk(clk), .rst_n(rst_n));
    // AXI interface for manager and subordinate
    `AXI_INTF a_if (.ACLK(clk), .ARESETn(rst_n));

    // --------------------------------------------------
    initial begin
        uvm_config_db#(virtual     `AXI_INTF.MANAGER)::set(uvm_root::get(), "uvm_test_top.env.axi_m", "axi_dvr_vif", a_if.MANAGER);
        uvm_config_db#(virtual `AXI_INTF.SUBORDINATE)::set(uvm_root::get(), "uvm_test_top.env.axi_s", "axi_dvr_vif", a_if.SUBORDINATE);
        uvm_config_db#(virtual             `AXI_INTF)::set(uvm_root::get(), "uvm_test_top.env",       "axi_mon_vif", a_if);
        uvm_config_db#(virtual          testbench_if)::set(uvm_root::get(), "uvm_test_top.env",       "tb_vif",      tb_if);

        run_test();
    end

    // --------------------------------------------------
    initial begin
        $dumpfile("wave.vcd");
        $dumpvars(0, "tb_top");
    end

`include "verilator_trace_workaround.svh"
endmodule