# Logging control
LOG_REDIR = >&
TIME=/usr/bin/time --format "Elapsed: %E, Memory: %M KB [Swaps %W]"

# Makefile variables
# NUM_PROCS=$(shell nproc --all)
NUM_PROCS=6
PROJ_BASE=$(shell pwd)

# Make and run project
UVM_HOME=$(HOME)/git/uvm-verilator
PROJ=axi

SV_OUT=obj_dir/Vuvm_pkg__verFiles.dat
SV_BUILD_LOG=logs/$(PROJ)_build_sv.log

CPP_OUT=$(PROJ).sim
CPP_BUILD_LOG=logs/$(PROJ)_build_cpp.log

SIM_LOG=$(PROJ)_sim.log

SV_FILES=$(shell ls common/*.sv src/axi/*.sv tb/*.sv)
SV_SRC=$(UVM_HOME)/src/uvm_pkg.sv common/common_pkg.sv src/axi/axi_types.sv src/axi/axi_pkg.sv tb/tb_pkg.sv
DPI_SRC=$(UVM_HOME)/src/dpi/uvm_dpi.cc
DPI_INC=-I/usr/share/verilator/include
SV_DEPS=$(SV_FILES)

CPP_SRC=sim_$(PROJ).cpp

TIMESCALE= --timescale '1ns/1ns'

ifndef VERI_TRACE_DIS
TB_DEFINES=+define+VERI_TRACE_EN
endif
UVM_DEFINES=+define+UVM_NO_DPI \
            +define+UVM_REPORT_DISABLE_FILE_LINE
DISABLED_WARNINGS=-Wno-WIDTHTRUNC  -Wno-WIDTHEXPAND \
                  -Wno-CASTCONST   -Wno-CONSTRAINTIGN \
                  -Wno-MISINDENT   -Wno-REALCVT \
                  -Wno-SYMRSVDWORD -Wno-CASEINCOMPLETE

BUILD_ARGS=-I$(UVM_HOME)/src -I. \
        -o $(PROJ).sim \
        -j $(NUM_PROCS) \
        --error-limit 10 \
        --timing $(TIMESCALE) \
        --trace \
        --top tb_top \
        +define+SVA_ON \
        $(TB_DEFINES) \
        $(UVM_DEFINES) \
        $(DISABLED_WARNINGS) \
        +incdir+common +incdir+src/axi +incdir+tb \
        $(SV_SRC)

ifndef TEST_NAME
    TEST_NAME=test_basic
endif

#
# Full build to generate testbench executable (Default target)
#
build: build_cpp
	@echo "Build done"

prepare_area:
	$(info #----------------)
	$(info # Preparing area)
	$(info #----------------)
	@if [ ! -d $(PROJ_BASE)/logs ]; then mkdir -p $(PROJ_BASE)/logs; fi

#
# C code generation from SystemVerilog
#
build_sv: prepare_area $(SV_OUT)

$(PROJ_BASE)/logs:
	@if [ ! -d $(PROJ_BASE)/logs ]; then mkdir -p $(PROJ_BASE)/logs; fi

$(SV_OUT): $(PROJ_BASE)/logs $(SV_DEPS)
	$(info #------------)
	$(info # Building SV)
	$(info #------------)
	@verilator --cc $(BUILD_ARGS)

#
# C code build to generate testbench executable
#
build_cpp: build_sv $(CPP_OUT)

$(CPP_OUT): $(SV_OUT)
	$(info #-------------)
	$(info # Building CPP)
	$(info #-------------)
	@verilator --binary $(BUILD_ARGS)

#
# Run just lint to detect syntax errors during development
#
lint:
	$(info #--------)
	$(info # Linting)
	$(info #--------)
	@verilator --lint-only $(BUILD_ARGS)

#
# Run test. Use TEST_NAME=<test name> on make line to pick the test
#
run: $(CPP_OUT)
	$(info #---------------------)
	$(info # Running $(TEST_NAME))
	$(info #---------------------)
	@if [ ! -d runs/$(TEST_NAME) ]; then mkdir -p runs/$(TEST_NAME); fi
	@cd runs/$(TEST_NAME) && \
        $(PROJ_BASE)/obj_dir/$(PROJ).sim +UVM_TESTNAME=$(TEST_NAME) +UVM_CONFIG_DB_TRACE |& tee $(SIM_LOG)
	notify-send "[$(PROJ)] Test run done"

#
# Remove generated files
# - This will not remove 'runs' directory that contains simulation run logs
#
clean:
	rm -rf obj_dir logs $(PROJ)*.log