// Testbench interface for UVM-based verification environment
interface testbench_if (
    input clk,
    virtual axi_intf #(.ADDR_WIDTH(`ADDR_WIDTH),
               .CEIL_DATA_WIDTH_DIV_128(`CEIL_DATA_WIDTH_DIV_128),
               .CEIL_DATA_WIDTH_DIV_128_TMS_4(`CEIL_DATA_WIDTH_DIV_128_TMS_4),
               .CEIL_DATA_WIDTH_DIV_64(`CEIL_DATA_WIDTH_DIV_64),
               .DATA_WIDTH(`DATA_WIDTH),
               .DATA_WIDTH_DIV_8(`DATA_WIDTH_DIV_8)) m_if,
    virtual axi_intf #(.ADDR_WIDTH(`ADDR_WIDTH),
               .CEIL_DATA_WIDTH_DIV_128(`CEIL_DATA_WIDTH_DIV_128),
               .CEIL_DATA_WIDTH_DIV_128_TMS_4(`CEIL_DATA_WIDTH_DIV_128_TMS_4),
               .CEIL_DATA_WIDTH_DIV_64(`CEIL_DATA_WIDTH_DIV_64),
               .DATA_WIDTH(`DATA_WIDTH),
               .DATA_WIDTH_DIV_8(`DATA_WIDTH_DIV_8)) s_if);

    logic rst_n;

    initial begin
        forever begin
            @(clk or rst_n);
                $monitor("@%6t: %b %b ", $time,
                    rst_n, clk);
        end
    end
endinterface