// Testbench top module for UVM-based verification environment
import uvm_pkg::*;

module tb_top (input logic sys_clk);
    logic clk;
    logic rst_n;

    // AXI interface for manager and subordinate
    `AXI_INTF a_if (.ACLK(clk), .ARESETn(rst_n));

    // // Instantiate the UVM testbench interface
    // testbench_if tb_if (
    //     .clk(clk),
    //     .m_if(m_if),
    //     .s_if(s_if)
    // );
    // assign tb_if.rst_n = rst_n;

    // --------------------------------------------------
    initial begin
        uvm_config_db#(virtual     `AXI_INTF.MANAGER)::set(uvm_root::get(), "uvm_test_top.env.axi_m", "axi_dvr_vif", a_if.MANAGER);
        uvm_config_db#(virtual `AXI_INTF.SUBORDINATE)::set(uvm_root::get(), "uvm_test_top.env.axi_s", "axi_dvr_vif", a_if.SUBORDINATE);
        uvm_config_db#(virtual             `AXI_INTF)::set(uvm_root::get(), "uvm_test_top.env",       "axi_mon_vif", a_if);

        run_test();
    end

    // --------------------------------------------------
    initial begin
        $dumpfile("wave.vcd");
        $dumpvars(0, "tb_top");
    end

    // --------------------------------------------------
    // Clock generation
    // TODO: Move to interface. Parameterize frequency
    initial begin
        clk = 0; // Initialize clock to 0 at time 0
        forever begin
            #5ns clk = ~clk; // Toggle clock every 5 ns
        end
    end

    // --------------------------------------------------
    initial begin
        rst_n = 0;

        #20ns rst_n = 1; // Release reset after 20 ns
    end
endmodule