125 lines
3.0 KiB
Makefile
125 lines
3.0 KiB
Makefile
# Logging control
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LOG_REDIR = >&
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TIME=/usr/bin/time --format "Elapsed: %E, Memory: %M KB [Swaps %W]"
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# Makefile variables
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# NUM_PROCS=$(shell nproc --all)
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NUM_PROCS=6
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PROJ_BASE=$(shell pwd)
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# Make and run project
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UVM_HOME=$(HOME)/git/uvm-verilator
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PROJ=axi
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SV_OUT=obj_dir/Vuvm_pkg__verFiles.dat
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SV_BUILD_LOG=logs/$(PROJ)_build_sv.log
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CPP_OUT=$(PROJ).sim
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CPP_BUILD_LOG=logs/$(PROJ)_build_cpp.log
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SIM_LOG=$(PROJ)_sim.log
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SV_FILES=$(shell ls common/*.sv src/axi/*.sv tb/*.sv)
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SV_SRC=$(UVM_HOME)/src/uvm_pkg.sv common/common_pkg.sv src/axi/axi_types.sv src/axi/axi_pkg.sv tb/tb_pkg.sv
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DPI_SRC=$(UVM_HOME)/src/dpi/uvm_dpi.cc
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DPI_INC=-I/usr/share/verilator/include
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SV_DEPS=$(SV_FILES)
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CPP_SRC=sim_$(PROJ).cpp
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TIMESCALE= --timescale '1ns/1ns'
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ifndef VERI_TRACE_DIS
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TB_DEFINES=+define+VERI_TRACE_EN
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endif
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UVM_DEFINES=+define+UVM_NO_DPI \
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+define+UVM_REPORT_DISABLE_FILE_LINE
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DISABLED_WARNINGS=-Wno-WIDTHTRUNC -Wno-WIDTHEXPAND \
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-Wno-CASTCONST -Wno-CONSTRAINTIGN \
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-Wno-MISINDENT -Wno-REALCVT \
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-Wno-SYMRSVDWORD -Wno-CASEINCOMPLETE
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BUILD_ARGS=-I$(UVM_HOME)/src -I. \
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-o $(PROJ).sim \
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-j $(NUM_PROCS) \
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--error-limit 10 \
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--timing $(TIMESCALE) \
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--trace \
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--x-initial 0 \
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--top tb_top \
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+define+SVA_ON \
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$(TB_DEFINES) \
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$(UVM_DEFINES) \
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$(DISABLED_WARNINGS) \
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+incdir+common +incdir+src/axi +incdir+tb \
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$(SV_SRC)
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ifndef TEST_NAME
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TEST_NAME=test_basic
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endif
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#
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# Full build to generate testbench executable (Default target)
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#
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build: build_cpp
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@echo "Build done"
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prepare_area:
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$(info #----------------)
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$(info # Preparing area)
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$(info #----------------)
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@if [ ! -d $(PROJ_BASE)/logs ]; then mkdir -p $(PROJ_BASE)/logs; fi
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#
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# C code generation from SystemVerilog
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#
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build_sv: prepare_area $(SV_OUT)
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$(PROJ_BASE)/logs:
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@if [ ! -d $(PROJ_BASE)/logs ]; then mkdir -p $(PROJ_BASE)/logs; fi
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$(SV_OUT): $(PROJ_BASE)/logs $(SV_DEPS)
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$(info #------------)
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$(info # Building SV)
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$(info #------------)
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@verilator --cc $(BUILD_ARGS)
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#
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# C code build to generate testbench executable
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#
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build_cpp: build_sv $(CPP_OUT)
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$(CPP_OUT): $(SV_OUT)
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$(info #-------------)
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$(info # Building CPP)
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$(info #-------------)
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@verilator --binary $(BUILD_ARGS)
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#
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# Run just lint to detect syntax errors during development
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#
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lint:
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$(info #--------)
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$(info # Linting)
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$(info #--------)
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@verilator --lint-only $(BUILD_ARGS)
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#
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# Run test. Use TEST_NAME=<test name> on make line to pick the test
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#
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run: $(CPP_OUT)
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$(info #---------------------)
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$(info # Running $(TEST_NAME))
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$(info #---------------------)
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@if [ ! -d runs/$(TEST_NAME) ]; then mkdir -p runs/$(TEST_NAME); fi
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@cd runs/$(TEST_NAME) && \
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$(PROJ_BASE)/obj_dir/$(PROJ).sim +verilator+seed+2 +UVM_TESTNAME=$(TEST_NAME) +UVM_CONFIG_DB_TRACE |& tee $(SIM_LOG)
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notify-send "[$(PROJ)] Test run done"
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#
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# Remove generated files
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# - This will not remove 'runs' directory that contains simulation run logs
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#
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clean:
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rm -rf obj_dir logs $(PROJ)*.log
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