Mahesh Asolkar
800e9c4008
* Bare skeleton implementation of everything * Testbench builds with Verilator * Test runs
41 lines
1.5 KiB
Systemverilog
41 lines
1.5 KiB
Systemverilog
// Testbench environment for UVM-based verification
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class tb_env extends uvm_env;
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axi_agent axi_m;
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axi_agent axi_s;
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`uvm_component_utils(tb_env)
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// ------------------------------------------------------------
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function new(string name, uvm_component parent);
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super.new(name, parent);
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endfunction
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// ------------------------------------------------------------
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virtual function void build_phase(uvm_phase phase);
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axi_m = axi_agent::type_id::create("axi_m", this);
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axi_s = axi_agent::type_id::create("axi_s", this);
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`uvm_info("tb_env", $sformatf("Building testbench environment: %s", get_full_name()), UVM_LOW)
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// Set agent types in AXI agents
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axi_m.set_agent_type(MANAGER);
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axi_s.set_agent_type(SUBORDINATE);
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endfunction
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// ------------------------------------------------------------
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virtual function void connect_phase(uvm_phase phase);
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`uvm_info("tb_env", $sformatf("Connecting testbench environment: %s", get_full_name()), UVM_LOW)
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endfunction
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// ------------------------------------------------------------
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virtual function void report_phase(uvm_phase phase);
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`uvm_info("tb_env", $sformatf("Reporting for testbench environment: %s", get_full_name()), UVM_LOW)
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// Add any specific report phase tasks here
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endfunction
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// ------------------------------------------------------------
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function uvm_sequencer_base get_axi_m_sequencer();
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return axi_m.sequencer;
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endfunction
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endclass : tb_env
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