20 lines
340 B
Systemverilog
20 lines
340 B
Systemverilog
`include "tb_intf.sv"
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package tb_pkg;
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import uvm_pkg::*;
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import common_pkg::*;
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import axi_pkg::*;
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import axi_types::*;
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`include "uvm_macros.svh"
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// UVM components
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`include "tb_env.sv"
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// UVM sequences
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`include "tb_seq_base.sv"
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// Tests
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`include "test_base.sv"
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endpackage
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`include "tb_top.sv"
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