9 lines
436 B
Systemverilog
9 lines
436 B
Systemverilog
// Convenience macros for AXI interfaces
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`define AXI_INTF axi_intf #(.ADDR_WIDTH(`ADDR_WIDTH), \
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.CEIL_DATA_WIDTH_DIV_128(`CEIL_DATA_WIDTH_DIV_128), \
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.CEIL_DATA_WIDTH_DIV_128_TMS_4(`CEIL_DATA_WIDTH_DIV_128_TMS_4), \
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.CEIL_DATA_WIDTH_DIV_64(`CEIL_DATA_WIDTH_DIV_64), \
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.DATA_WIDTH(`DATA_WIDTH), \
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.DATA_WIDTH_DIV_8(`DATA_WIDTH_DIV_8))
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