54 lines
1.4 KiB
Systemverilog
54 lines
1.4 KiB
Systemverilog
// Base sequence class for testbench sequences
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class tb_seq_base extends uvm_sequence;
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`uvm_object_utils(tb_seq_base)
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// Constructor
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function new(string name = "tb_seq_base");
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super.new(name);
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endfunction
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endclass : tb_seq_base
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// ----------------------------------------------------------------------
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class axi_m_seq_base extends tb_seq_base;
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tb_env env;
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`uvm_object_utils(axi_m_seq_base)
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// Constructor
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function new(string name = "axi_m_seq_base");
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super.new(name);
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endfunction
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// Task to start the sequence
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virtual task body();
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bit ok = uvm_config_db#(tb_env)::get(uvm_root::get(), "*", "env", env);
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endtask
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endclass : axi_m_seq_base
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// ----------------------------------------------------------------------
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class axi_simple_seq extends axi_m_seq_base;
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`uvm_object_utils(axi_simple_seq)
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// Constructor
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function new(string name = "axi_simple_seq");
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super.new(name);
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endfunction
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// Task to start the sequence
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virtual task body();
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axi_transaction txn;
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super.body();
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`uvm_info("axi_simple_seq", "Starting simple AXI sequence", UVM_LOW)
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repeat(10) begin
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`uvm_do(txn, env.get_axi_m_sequencer(), -1, {
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addr != {`ADDR_WIDTH{1'b0}};
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data != {`DATA_WIDTH{1'b0}};
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strb == 'hf; // Example byte enable
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});
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end
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endtask
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endclass : axi_simple_seq
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