sample_uvm_tb/uvm_tb.sv

// -----
//
// Copyright (c) 2024 Mahesh Asolkar
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of
// this software and associated documentation files (the "Software"), to deal in
// the Software without restriction, including without limitation the rights to
// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is furnished to do
// so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
// -----
// uvm_tb in SystemVerilog
import uvm_pkg::*;

module uvm_tb (input logic sys_clk);
    logic clk;
    logic rst_n;
    logic [31:0] d1_data_i;
    logic [31:0] d1_data_o;
    logic [31:0] d2_data_i;
    logic [31:0] d2_data_o;

    design_if d1_if(.clk(clk));
    assign d1_if.rst_n = rst_n;
    assign d1_if.data_in = d1_data_i;
    assign d1_data_o = d1_if.data_out;

    design_if d2_if(.clk(clk));
    assign d2_if.rst_n = rst_n;
    assign d2_if.data_in = d2_data_i;
    assign d2_data_o = d2_if.data_out;

    testbench_if uvm_tb_if(
        .clk(clk),
        .d1_if(d1_if),
        .d2_if(d2_if)
    );
    assign rst_n = uvm_tb_if.rst_n;

    rtl_design d1(d1_if.DN);

    rtl_design d2(d2_if.DN);

    initial begin
        // TbEnv t = new(.name("uvm_tbTbEnv"), .parent(null));
        //               // .intf(uvm_tb_if.TB));

        // t.set_handles(uvm_tb_if);
        // // t.run_phase();

        // $display("Simulation with UVM done at %t", $time);
        // $finish;

        uvm_config_db#(virtual testbench_if)::set(uvm_root::get(), "*", "tb_vif", uvm_tb_if);

        run_test();
    end

    //  initial begin
    //      $dumpfile("wave.vcd");
    //      $dumpvars();
    //  end

    // TODO: Move to interface. Parameterize frequency
    always #5 clk = ~clk;
endmodule