2024-12-26 22:31:55 -08:00
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# Sample UVM testbench
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2024-12-28 03:44:50 +00:00
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This is a simple playground testbench. It is written in SystemVerilog using UVM framework.
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2024-12-26 22:31:55 -08:00
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2024-12-28 03:44:50 +00:00
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`Makefile` uses the [Verilator](https://www.veripool.org/verilator/) simulator to build and run the testbench.
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## UVM for Verilator
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* This testbench uses UVM modified to work with Verilator. This comes from project maintained by good folks at [Antmicro](https://antmicro.com/).
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```shell
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% git clone https://github.com/antmicro/uvm-verilator.git -b current-patches-2
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```
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