sample_uvm_tb/testbench_env.sv

// -----
//
// Copyright (c) 2024 Mahesh Asolkar
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of
// this software and associated documentation files (the "Software"), to deal in
// the Software without restriction, including without limitation the rights to
// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is furnished to do
// so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
// -----
// Top class
class testbench_env extends uvm_component;
    string name;
    virtual testbench_if tb_if;

    agent_reset rst_agt;
    sequencer_tb tb_sequencer;

    `uvm_component_utils(testbench_env)

    // ------------------------------------------------------------
    function new(string name, uvm_component parent);
        super.new(name, parent);
        `uvm_info("new", $sformatf("Initialized testbench %s", name), UVM_LOW)
    endfunction

    // ------------------------------------------------------------
    function void build_phase(uvm_phase phase);
        super.build_phase(phase);

        rst_agt = agent_reset::type_id::create("reset_agent", this);
        tb_sequencer  = sequencer_tb::type_id::create("tb_sequencer", this);
    endfunction

    // ------------------------------------------------------------
    function void connect_phase(uvm_phase phase);
        super.connect_phase(phase);

        if (!uvm_config_db#(virtual testbench_if)::get(this, "", "tb_vif", tb_if)) begin
            `uvm_fatal("CFG_DB_FAIL", $sformatf("Failed to fetch interface for %0s", get_full_name()))
        end

        `uvm_info("connect_phase", $sformatf("Build phase complete"), UVM_LOW)
    endfunction

    // ------------------------------------------------------------
    function uvm_sequencer get_tb_sequencer();
        return tb_sequencer;
    endfunction

    // ------------------------------------------------------------
    function uvm_sequencer get_rst_sequencer();
        return rst_agt.sequencer;
    endfunction
endclass