From 2554b628739953fe5725a18b1190e86f66816d00 Mon Sep 17 00:00:00 2001
From: Mahesh Asolkar <mahesh@mahesha.com>
Date: Thu, 26 Dec 2024 22:31:55 -0800
Subject: [PATCH] Initial README

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+# Sample UVM testbench
+
+This is a simple testbench using UVM framework.
+
+`Makefile` uses the Verilator simulator to build and run the testbench.