From 5734ab7ba13ecc602b68e8c980b9b6fbbd2564a5 Mon Sep 17 00:00:00 2001 From: Mahesh Asolkar Date: Sat, 28 Dec 2024 03:44:50 +0000 Subject: [PATCH] Added more verilator and UVM specifics to README --- README.md | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 0546327..3f8caad 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,13 @@ # Sample UVM testbench -This is a simple testbench using UVM framework. +This is a simple playground testbench. It is written in SystemVerilog using UVM framework. -`Makefile` uses the Verilator simulator to build and run the testbench. +`Makefile` uses the [Verilator](https://www.veripool.org/verilator/) simulator to build and run the testbench. + +## UVM for Verilator + +* This testbench uses UVM modified to work with Verilator. This comes from project maintained by good folks at [Antmicro](https://antmicro.com/). + +```shell + % git clone https://github.com/antmicro/uvm-verilator.git -b current-patches-2 +``` \ No newline at end of file