// Some simple design

module rtl_design(design_if intf);

    logic [31:0] data_out_drv = 0;
    assign intf.data_out = data_out_drv;

    string trk_name;
    integer trk_h;

    initial begin
        data_out_drv = 32'h0;
    end

    always @(posedge intf.clk) begin
        if (intf.rst_n) begin
            data_out_drv = intf.data_in;
        end
    end

    always_latch @(intf.rst_n) begin
        if (!intf.rst_n) begin
            data_out_drv = 32'h0;
        end
    end

    initial begin
        trk_name = $sformatf("%m.out");
        trk_h = $fopen(trk_name, "w");
        $fdisplay(trk_h, "Tracker: %s", trk_name);
        $display("Starting tracker: %s", trk_name);
        $fmonitor(trk_h, "@%6t: %b %b %h %h", $time,
            intf.rst_n, intf.clk, intf.data_in, intf.data_out);
    end

    function void be_done();
        $display("Closing tracker %s", trk_name);
        $fclose(trk_h);
    endfunction
endmodule