// Design and Testbench interfaces
interface design_if (
    input clk);

    logic        rst_n;
    logic [31:0] data_in;
    logic [31:0] data_out;

    modport DN (output data_out,      input  rst_n, clk, data_in);
    modport TB (input  clk, data_out, output rst_n, data_in);
endinterface

interface testbench_if (
    input clk,
    virtual design_if d1_if,
    virtual design_if d2_if);

    logic rst_n;

    modport DN (input  rst_n, clk);
    modport TB (input  clk, output rst_n);
endinterface