class seq_base extends uvm_sequence; testbench_env tb_env; `uvm_object_utils(seq_base) function new(string name = "seq_base"); super.new(name); endfunction function void set_handles(testbench_env env); tb_env = env; endfunction virtual task body(); bit ok = uvm_config_db#(testbench_env)::get(m_sequencer, "", "tb_env", tb_env); endtask endclass class seq_basic extends seq_base; `uvm_object_utils(seq_basic) function new(string name = "seq_basic"); super.new(name); endfunction virtual task body(); super.body(); `uvm_info("body", $sformatf("Initiating stimulus ..."), UVM_LOW) fork begin d_stimulus(tb_env.tb_if.d1_if, 1); end begin d_stimulus(tb_env.tb_if.d2_if, 2); end join `uvm_info("body", $sformatf("Stimulus done."), UVM_LOW) endtask task d_stimulus(virtual design_if d_if, int inst_n); `uvm_info("d_stimulus", $sformatf("Inst-%0d: Initiating stimulus...", inst_n), UVM_LOW); repeat(20) @(negedge tb_env.tb_if.clk); d_if.data_in = {inst_n[15:0], 16'hd1}; `uvm_info("d_stimulus", $sformatf("Inst-%0d: Driving data_in=0x%h", inst_n, d_if.data_in), UVM_LOW); repeat(50) @(negedge tb_env.tb_if.clk); d_if.data_in = {inst_n[15:0], 16'hd2}; `uvm_info("d_stimulus", $sformatf("Inst-%0d: Driving data_in=0x%h", inst_n, d_if.data_in), UVM_LOW); repeat(20) @(negedge tb_env.tb_if.clk); `uvm_info("d_stimulus", $sformatf("Inst-%0d: ... stimulus done", inst_n), UVM_LOW); endtask endclass class seq_reset extends seq_base; `uvm_object_utils(seq_reset) function new(string name = "seq_reset"); super.new(name); endfunction virtual task body(); super.body(); `uvm_info("body", $sformatf("Initiating reset..."), UVM_LOW) tb_env.tb_if.rst_n = 0; repeat(10) @(posedge tb_env.tb_if.clk); tb_env.tb_if.rst_n = 1; `uvm_info("body", $sformatf("Reset done."), UVM_LOW) endtask endclass