79 lines
2.4 KiB
Systemverilog
79 lines
2.4 KiB
Systemverilog
// -----
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//
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// Copyright (c) 2024 Mahesh Asolkar
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of
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// this software and associated documentation files (the "Software"), to deal in
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// the Software without restriction, including without limitation the rights to
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// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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// of the Software, and to permit persons to whom the Software is furnished to do
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// so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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//
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// -----
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// uvm_tb in SystemVerilog
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import uvm_pkg::*;
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module uvm_tb (input logic sys_clk);
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logic clk;
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logic rst_n;
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logic [31:0] d1_data_i;
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logic [31:0] d1_data_o;
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logic [31:0] d2_data_i;
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logic [31:0] d2_data_o;
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design_if d1_if(.clk(clk));
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assign d1_if.rst_n = rst_n;
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assign d1_if.data_in = d1_data_i;
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assign d1_data_o = d1_if.data_out;
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design_if d2_if(.clk(clk));
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assign d2_if.rst_n = rst_n;
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assign d2_if.data_in = d2_data_i;
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assign d2_data_o = d2_if.data_out;
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testbench_if uvm_tb_if(
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.clk(clk),
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.d1_if(d1_if),
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.d2_if(d2_if)
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);
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assign rst_n = uvm_tb_if.rst_n;
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rtl_design d1(d1_if.DN);
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rtl_design d2(d2_if.DN);
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initial begin
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// TbEnv t = new(.name("uvm_tbTbEnv"), .parent(null));
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// // .intf(uvm_tb_if.TB));
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// t.set_handles(uvm_tb_if);
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// // t.run_phase();
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// $display("Simulation with UVM done at %t", $time);
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// $finish;
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uvm_config_db#(virtual testbench_if)::set(uvm_root::get(), "*", "tb_vif", uvm_tb_if);
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run_test();
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end
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// initial begin
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// $dumpfile("wave.vcd");
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// $dumpvars();
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// end
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// TODO: Move to interface. Parameterize frequency
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always #5 clk = ~clk;
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endmodule
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