Separated manager and subordinate drivers
Other clean up and changes
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@@ -42,10 +42,12 @@ class axi_simple_seq extends axi_m_seq_base;
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`uvm_info("axi_simple_seq", "Starting simple AXI sequence", UVM_LOW)
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`uvm_do(txn, env.get_axi_m_sequencer(), -1, {
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addr == 32'h0000_0000; // Example address
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data == 32'hDEAD_BEEF; // Example data
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strb == 'hf; // Example byte enable
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});
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repeat(10) begin
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`uvm_do(txn, env.get_axi_m_sequencer(), -1, {
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addr != {`ADDR_WIDTH{1'b0}};
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data != {`DATA_WIDTH{1'b0}};
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strb == 'hf; // Example byte enable
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});
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end
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endtask
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endclass : axi_simple_seq
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@@ -20,6 +20,7 @@ module tb_top (input logic sys_clk);
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initial begin
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uvm_config_db#(virtual `AXI_INTF.MANAGER)::set(uvm_root::get(), "uvm_test_top.env.axi_m", "axi_dvr_vif", a_if.MANAGER);
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uvm_config_db#(virtual `AXI_INTF.SUBORDINATE)::set(uvm_root::get(), "uvm_test_top.env.axi_s", "axi_dvr_vif", a_if.SUBORDINATE);
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uvm_config_db#(virtual `AXI_INTF)::set(uvm_root::get(), "uvm_test_top.env", "axi_mon_vif", a_if);
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run_test();
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end
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@@ -27,7 +28,7 @@ module tb_top (input logic sys_clk);
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// --------------------------------------------------
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initial begin
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$dumpfile("wave.vcd");
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$dumpvars();
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$dumpvars(0, "tb_top");
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end
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// --------------------------------------------------
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