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Miscellaneous makefile updates

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This commit is contained in:
Mahesh Asolkar
2025-12-28 18:03:50 -08:00
parent 36eedfb56d
commit 90dbd81844
1 changed files with 42 additions and 17 deletions
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59
Makefile
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@@ -3,12 +3,23 @@ LOG_REDIR = >&
TIME=/usr/bin/time --format "Elapsed: %E, Memory: %M KB [Swaps %W]" TIME=/usr/bin/time --format "Elapsed: %E, Memory: %M KB [Swaps %W]"
# Makefile variables # Makefile variables
# NUM_PROCS=$(shell nproc --all) # Use as many threads as possible while keeping 2 for IO, browsing, etc.
NUM_PROCS=6 # USE_PROCS = $(( $(shell nproc --all) - 2 ))
KEEP_PROCS=2
TOTAL_PROCS=$(shell nproc --all)
USE_PROCS=$(shell expr $(TOTAL_PROCS) - $(KEEP_PROCS))
PROJ_BASE=$(shell pwd) PROJ_BASE=$(shell pwd)
# Make and run project # Verilator setup
# VERILATOR_HOME=$(HOME)/git/verilator
VERILATOR_HOME=/usr/share/verilator
# UVM setup
UVM_HOME=$(HOME)/git/uvm-verilator UVM_HOME=$(HOME)/git/uvm-verilator
# UVM_HOME=$(HOME)/git/ca_uvm-verilator
# UVM_HOME=$(HOME)/git/1800.2-2017-1.0
# Make and run project
PROJ=axi PROJ=axi
SV_OUT=obj_dir/Vuvm_pkg__verFiles.dat SV_OUT=obj_dir/Vuvm_pkg__verFiles.dat
@@ -22,7 +33,7 @@ SIM_LOG=$(PROJ)_sim.log
SV_FILES=$(shell ls common/*.sv src/axi/*.sv tb/*.sv) SV_FILES=$(shell ls common/*.sv src/axi/*.sv tb/*.sv)
SV_SRC=$(UVM_HOME)/src/uvm_pkg.sv common/common_pkg.sv src/axi/axi_types.sv src/axi/axi_pkg.sv tb/tb_pkg.sv SV_SRC=$(UVM_HOME)/src/uvm_pkg.sv common/common_pkg.sv src/axi/axi_types.sv src/axi/axi_pkg.sv tb/tb_pkg.sv
DPI_SRC=$(UVM_HOME)/src/dpi/uvm_dpi.cc DPI_SRC=$(UVM_HOME)/src/dpi/uvm_dpi.cc
DPI_INC=-I/usr/share/verilator/include DPI_INC=-I$(VERILATOR_HOME)/include
SV_DEPS=$(SV_FILES) SV_DEPS=$(SV_FILES)
CPP_SRC=sim_$(PROJ).cpp CPP_SRC=sim_$(PROJ).cpp
@@ -41,7 +52,7 @@ DISABLED_WARNINGS=-Wno-WIDTHTRUNC -Wno-WIDTHEXPAND \
BUILD_ARGS=-I$(UVM_HOME)/src -I. \ BUILD_ARGS=-I$(UVM_HOME)/src -I. \
-o $(PROJ).sim \ -o $(PROJ).sim \
-j $(NUM_PROCS) \ -j $(USE_PROCS) \
--error-limit 10 \ --error-limit 10 \
--timing $(TIMESCALE) \ --timing $(TIMESCALE) \
--trace \ --trace \
@@ -79,10 +90,10 @@ $(PROJ_BASE)/logs:
@if [ ! -d $(PROJ_BASE)/logs ]; then mkdir -p $(PROJ_BASE)/logs; fi @if [ ! -d $(PROJ_BASE)/logs ]; then mkdir -p $(PROJ_BASE)/logs; fi
$(SV_OUT): $(PROJ_BASE)/logs $(SV_DEPS) $(SV_OUT): $(PROJ_BASE)/logs $(SV_DEPS)
$(info #------------) $(info #------------------------)
$(info # Building SV) $(info # Building SV ($(USE_PROCS) threads))
$(info #------------) $(info #------------------------)
@verilator --cc $(BUILD_ARGS) @$(VERILATOR_HOME)/bin/verilator --cc $(BUILD_ARGS)
# #
# C code build to generate testbench executable # C code build to generate testbench executable
@@ -90,10 +101,10 @@ $(SV_OUT): $(PROJ_BASE)/logs $(SV_DEPS)
build_cpp: build_sv $(CPP_OUT) build_cpp: build_sv $(CPP_OUT)
$(CPP_OUT): $(SV_OUT) $(CPP_OUT): $(SV_OUT)
$(info #-------------) $(info #-------------------------)
$(info # Building CPP) $(info # Building CPP ($(USE_PROCS) threads))
$(info #-------------) $(info #-------------------------)
@verilator --binary $(BUILD_ARGS) @$(VERILATOR_HOME)/bin/verilator --binary $(BUILD_ARGS)
# #
# Run just lint to detect syntax errors during development # Run just lint to detect syntax errors during development
@@ -102,20 +113,34 @@ lint:
$(info #--------) $(info #--------)
$(info # Linting) $(info # Linting)
$(info #--------) $(info #--------)
@verilator --lint-only $(BUILD_ARGS) @$(VERILATOR_HOME)/bin/verilator --lint-only $(BUILD_ARGS)
# #
# Run test. Use TEST_NAME=<test name> on make line to pick the test # Run test. Use TEST_NAME=<test name> on make line to pick the test
# #
run: $(CPP_OUT) #run: $(CPP_OUT)
run:
$(info #---------------------) $(info #---------------------)
$(info # Running $(TEST_NAME)) $(info # Running $(TEST_NAME))
$(info #---------------------) $(info #---------------------)
@if [ ! -d runs/$(TEST_NAME) ]; then mkdir -p runs/$(TEST_NAME); fi @if [ ! -d runs/$(TEST_NAME) ]; then mkdir -p runs/$(TEST_NAME); fi
@cd runs/$(TEST_NAME) && \ cd runs/$(TEST_NAME) && \
$(PROJ_BASE)/obj_dir/$(PROJ).sim +verilator+seed+2 +UVM_TESTNAME=$(TEST_NAME) +UVM_CONFIG_DB_TRACE |& tee $(SIM_LOG) $(PROJ_BASE)/obj_dir/$(PROJ).sim +verilator+seed+2 \
+UVM_TESTNAME=$(TEST_NAME) \
+UVM_VERBOSITY=UVM_MEDIUM \
+uvm_set_verbosity=uvm_test_top.*,_ALL_,UVM_MEDIUM,run \
+UVM_CONFIG_DB_TRACE |& tee $(SIM_LOG)
notify-send "[$(PROJ)] Test run done" notify-send "[$(PROJ)] Test run done"
build_and_run: $(CPP_OUT) run
$(info Build and Run done)
info:
$(info #----------------------)
$(info # Procs: $(TOTAL_PROCS))
$(info # Keep: $(KEEP_PROCS))
$(info # Threads: $(USE_PROCS))
$(info #----------------------)
# #
# Remove generated files # Remove generated files
# - This will not remove 'runs' directory that contains simulation run logs # - This will not remove 'runs' directory that contains simulation run logs