AXI interface regenerated

This commit is contained in:
2025-10-01 23:57:04 -07:00
parent cce61f687a
commit 9f14bc7ceb
3 changed files with 43 additions and 38 deletions

View File

@@ -85,6 +85,7 @@ interface axi_intf #(
// A2.1.1 Write request channel
logic WVALID; // Valid indicator [Manager]
logic WREADY; // Ready indicator [Subordinate]
logic [ID_W_WIDTH-1:0] WID; // Transaction identifier for the write channels [Manager]
logic [DATA_WIDTH-1:0] WDATA; // Write data [Manager]
logic [DATA_WIDTH_DIV_8-1:0] WSTRB; // Write data strobes [Manager]
logic [CEIL_DATA_WIDTH_DIV_128_TMS_4-1:0] WTAG; // Memory Tag [Manager]
@@ -210,6 +211,7 @@ interface axi_intf #(
// A2.1.1 Write request channel
output WVALID,
input WREADY,
output WID,
output WDATA,
output WSTRB,
output WTAG,
@@ -336,6 +338,7 @@ interface axi_intf #(
// A2.1.1 Write request channel
input WVALID,
output WREADY,
input WID,
input WDATA,
input WSTRB,
input WTAG,

View File

@@ -248,44 +248,44 @@ sub get_axi_intf_data {
'name' => 'A2.1.1 Write request channel',
'signals' => [
# n: name, w: width, s: source, d: description
{'n' =>'AWVALID','w' =>'1','s' =>'Manager','d' =>'Valid indicator' },
{'n' =>'AWREADY','w' =>'1','s' =>'Subordinate','d' =>'Ready indicator' },
{'n' =>'AWID','w' =>'ID_W_WIDTH','s' =>'Manager','d' =>'Transaction identifier for the write channels' },
{'n' =>'AWADDR','w' =>'ADDR_WIDTH','s' =>'Manager','d' =>'Transaction address' },
{'n' =>'AWREGION','w' =>'4','s' =>'Manager','d' =>'Region identifier' },
{'n' =>'AWLEN','w' =>'8','s' =>'Manager','d' =>'Transaction length' },
{'n' =>'AWSIZE','w' =>'3','s' =>'Manager','d' =>'Transaction size' },
{'n' =>'AWBURST','w' =>'2','s' =>'Manager','d' =>'Burst attribute' },
{'n' =>'AWLOCK','w' =>'1','s' =>'Manager','d' =>'Exclusive access indicator' },
{'n' =>'AWCACHE','w' =>'4','s' =>'Manager','d' =>'Memory attributes' },
{'n' =>'AWPROT','w' =>'3','s' =>'Manager','d' =>'Access attributes' },
{'n' =>'AWNSE','w' =>'1','s' =>'Manager','d' =>'Non-secure extension bit for RME' },
{'n' =>'AWQOS','w' =>'4','s' =>'Manager','d' =>'QoS identifier' },
{'n' =>'AWUSER','w' =>'USER_REQ_WIDTH','s' =>'Manager','d' =>'User-defined extension to a request' },
{'n' =>'AWDOMAIN','w' =>'2','s' =>'Manager','d' =>'Shareability domain of a request' },
{'n' =>'AWSNOOP','w' =>'AWSNOOP_WIDTH','s' =>'Manager','d' =>'Write request opcode' },
{'n' =>'AWSTASHNID','w' =>'11','s' =>'Manager','d' =>'Stash Node ID' },
{'n' =>'AWSTASHNIDEN','w' =>'1','s' =>'Manager','d' =>'Stash Node ID enable' },
{'n' =>'AWSTASHLPID','w' =>'5','s' =>'Manager','d' =>'Stash Logical Processor ID' },
{'n' =>'AWSTASHLPIDEN','w' =>'1','s' =>'Manager','d' =>'Stash Logical Processor ID enable' },
{'n' =>'AWTRACE','w' =>'1','s' =>'Manager','d' =>'Trace signal' },
{'n' =>'AWLOOP','w' =>'LOOP_W_WIDTH','s' =>'Manager','d' =>'Loopback signals on the write channels' },
{'n' =>'AWMMUVALID','w' =>'1','s' =>'Manager','d' =>'MMU signal qualifier' },
{'n' =>'AWMMUSECSID','w' =>'SECSID_WIDTH','s' =>'Manager','d' =>'Secure Stream ID' },
{'n' =>'AWMMUSID','w' =>'SID_WIDTH','s' =>'Manager','d' =>'StreamID' },
{'n' =>'AWMMUSSIDV','w' =>'1','s' =>'Manager','d' =>'SubstreamID valid' },
{'n' =>'AWMMUSSID','w' =>'SSID_WIDTH','s' =>'Manager','d' =>'SubstreamID' },
{'n' =>'AWMMUATST','w' =>'1','s' =>'Manager','d' =>'Address translated indicator' },
{'n' =>'AWMMUFLOW','w' =>'2','s' =>'Manager','d' =>'SMMU flow type' },
{'n' =>'AWPBHA','w' =>'4','s' =>'Manager','d' =>'Page-based Hardware Attributes' },
{'n' =>'AWNSAID','w' =>'4','s' =>'Manager','d' =>'Non-secure Access ID' },
{'n' =>'AWSUBSYSID','w' =>'SUBSYSID_WIDTH','s' =>'Manager','d' =>'Subsystem ID' },
{'n' =>'AWATOP','w' =>'6','s' =>'Manager','d' =>'Atomic transaction opcode' },
{'n' =>'AWMPAM','w' =>'MPAM_WIDTH','s' =>'Manager','d' =>'MPAM information with a request' },
{'n' =>'AWIDUNQ','w' =>'1','s' =>'Manager','d' =>'Unique ID indicator' },
{'n' =>'AWCMO','w' =>'AWCMO_WIDTH','s' =>'Manager','d' =>'CMO type' },
{'n' =>'AWTAGOP','w' =>'2','s' =>'Manager','d' =>'Memory Tag operation for write requests' },
{'n' =>'AWMECID','w' =>'MECID_WIDTH','s' =>'Manager','d' =>'Memory Encryption Context identifier' },
{ 'n' => 'AWVALID','w' => '1','s' => 'Manager','d' => 'Valid indicator' },
{ 'n' => 'AWREADY','w' => '1','s' => 'Subordinate','d' => 'Ready indicator' },
{ 'n' => 'AWID','w' => 'ID_W_WIDTH','s' => 'Manager','d' => 'Transaction identifier for the write channels' },
{ 'n' => 'AWADDR','w' => 'ADDR_WIDTH','s' => 'Manager','d' => 'Transaction address' },
{ 'n' => 'AWREGION','w' => '4','s' => 'Manager','d' => 'Region identifier' },
{ 'n' => 'AWLEN','w' => '8','s' => 'Manager','d' => 'Transaction length' },
{ 'n' => 'AWSIZE','w' => '3','s' => 'Manager','d' => 'Transaction size' },
{ 'n' => 'AWBURST','w' => '2','s' => 'Manager','d' => 'Burst attribute' },
{ 'n' => 'AWLOCK','w' => '1','s' => 'Manager','d' => 'Exclusive access indicator' },
{ 'n' => 'AWCACHE','w' => '4','s' => 'Manager','d' => 'Memory attributes' },
{ 'n' => 'AWPROT','w' => '3','s' => 'Manager','d' => 'Access attributes' },
{ 'n' => 'AWNSE','w' => '1','s' => 'Manager','d' => 'Non-secure extension bit for RME' },
{ 'n' => 'AWQOS','w' => '4','s' => 'Manager','d' => 'QoS identifier' },
{ 'n' => 'AWUSER','w' => 'USER_REQ_WIDTH','s' => 'Manager','d' => 'User-defined extension to a request' },
{ 'n' => 'AWDOMAIN','w' => '2','s' => 'Manager','d' => 'Shareability domain of a request' },
{ 'n' => 'AWSNOOP','w' => 'AWSNOOP_WIDTH','s' => 'Manager','d' => 'Write request opcode' },
{ 'n' => 'AWSTASHNID','w' => '11','s' => 'Manager','d' => 'Stash Node ID' },
{ 'n' => 'AWSTASHNIDEN','w' => '1','s' => 'Manager','d' => 'Stash Node ID enable' },
{ 'n' => 'AWSTASHLPID','w' => '5','s' => 'Manager','d' => 'Stash Logical Processor ID' },
{ 'n' => 'AWSTASHLPIDEN','w' => '1','s' => 'Manager','d' => 'Stash Logical Processor ID enable' },
{ 'n' => 'AWTRACE','w' => '1','s' => 'Manager','d' => 'Trace signal' },
{ 'n' => 'AWLOOP','w' => 'LOOP_W_WIDTH','s' => 'Manager','d' => 'Loopback signals on the write channels' },
{ 'n' => 'AWMMUVALID','w' => '1','s' => 'Manager','d' => 'MMU signal qualifier' },
{ 'n' => 'AWMMUSECSID','w' => 'SECSID_WIDTH','s' => 'Manager','d' => 'Secure Stream ID' },
{ 'n' => 'AWMMUSID','w' => 'SID_WIDTH','s' => 'Manager','d' => 'StreamID' },
{ 'n' => 'AWMMUSSIDV','w' => '1','s' => 'Manager','d' => 'SubstreamID valid' },
{ 'n' => 'AWMMUSSID','w' => 'SSID_WIDTH','s' => 'Manager','d' => 'SubstreamID' },
{ 'n' => 'AWMMUATST','w' => '1','s' => 'Manager','d' => 'Address translated indicator' },
{ 'n' => 'AWMMUFLOW','w' => '2','s' => 'Manager','d' => 'SMMU flow type' },
{ 'n' => 'AWPBHA','w' => '4','s' => 'Manager','d' => 'Page-based Hardware Attributes' },
{ 'n' => 'AWNSAID','w' => '4','s' => 'Manager','d' => 'Non-secure Access ID' },
{ 'n' => 'AWSUBSYSID','w' => 'SUBSYSID_WIDTH','s' => 'Manager','d' => 'Subsystem ID' },
{ 'n' => 'AWATOP','w' => '6','s' => 'Manager','d' => 'Atomic transaction opcode' },
{ 'n' => 'AWMPAM','w' => 'MPAM_WIDTH','s' => 'Manager','d' => 'MPAM information with a request' },
{ 'n' => 'AWIDUNQ','w' => '1','s' => 'Manager','d' => 'Unique ID indicator' },
{ 'n' => 'AWCMO','w' => 'AWCMO_WIDTH','s' => 'Manager','d' => 'CMO type' },
{ 'n' => 'AWTAGOP','w' => '2','s' => 'Manager','d' => 'Memory Tag operation for write requests' },
{ 'n' => 'AWMECID','w' => 'MECID_WIDTH','s' => 'Manager','d' => 'Memory Encryption Context identifier' },
]
},
{
@@ -293,6 +293,7 @@ sub get_axi_intf_data {
'signals' => [
{ 'n' => 'WVALID', 'w' => '1', 's' => 'Manager', 'd' => 'Valid indicator' },
{ 'n' => 'WREADY', 'w' => '1', 's' => 'Subordinate', 'd' => 'Ready indicator' },
{ 'n' => 'WID','w' => 'ID_W_WIDTH','s' => 'Manager','d' => 'Transaction identifier for the write channels' },
{ 'n' => 'WDATA', 'w' => 'DATA_WIDTH', 's' => 'Manager', 'd' => 'Write data' },
{ 'n' => 'WSTRB', 'w' => 'DATA_WIDTH_DIV_8', 's' => 'Manager', 'd' => 'Write data strobes' },
{ 'n' => 'WTAG', 'w' => 'CEIL_DATA_WIDTH_DIV_128_TMS_4', 's' => 'Manager', 'd' => 'Memory Tag' },

View File

@@ -49,6 +49,7 @@
// A2.1.1 Write request channel
always @(a_if.WVALID) t_if.WVALID <= a_if.WVALID;
always @(a_if.WREADY) t_if.WREADY <= a_if.WREADY;
always @(a_if.WID) t_if.WID <= a_if.WID;
always @(a_if.WDATA) t_if.WDATA <= a_if.WDATA;
always @(a_if.WSTRB) t_if.WSTRB <= a_if.WSTRB;
always @(a_if.WTAG) t_if.WTAG <= a_if.WTAG;