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AXI interface regenerated

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Mahesh Asolkar
2025-10-01 23:57:04 -07:00
parent cce61f687a
commit 9f14bc7ceb
3 changed files with 43 additions and 38 deletions
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3
common/axi.intf.sv
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@@ -85,6 +85,7 @@ interface axi_intf #(
// A2.1.1 Write request channel // A2.1.1 Write request channel
logic WVALID; // Valid indicator [Manager] logic WVALID; // Valid indicator [Manager]
logic WREADY; // Ready indicator [Subordinate] logic WREADY; // Ready indicator [Subordinate]
logic [ID_W_WIDTH-1:0] WID; // Transaction identifier for the write channels [Manager]
logic [DATA_WIDTH-1:0] WDATA; // Write data [Manager] logic [DATA_WIDTH-1:0] WDATA; // Write data [Manager]
logic [DATA_WIDTH_DIV_8-1:0] WSTRB; // Write data strobes [Manager] logic [DATA_WIDTH_DIV_8-1:0] WSTRB; // Write data strobes [Manager]
logic [CEIL_DATA_WIDTH_DIV_128_TMS_4-1:0] WTAG; // Memory Tag [Manager] logic [CEIL_DATA_WIDTH_DIV_128_TMS_4-1:0] WTAG; // Memory Tag [Manager]
@@ -210,6 +211,7 @@ interface axi_intf #(
// A2.1.1 Write request channel // A2.1.1 Write request channel
output WVALID, output WVALID,
input WREADY, input WREADY,
output WID,
output WDATA, output WDATA,
output WSTRB, output WSTRB,
output WTAG, output WTAG,
@@ -336,6 +338,7 @@ interface axi_intf #(
// A2.1.1 Write request channel // A2.1.1 Write request channel
input WVALID, input WVALID,
output WREADY, output WREADY,
input WID,
input WDATA, input WDATA,
input WSTRB, input WSTRB,
input WTAG, input WTAG,

1
scripts/gen_axi_intf.pl
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@@ -293,6 +293,7 @@ sub get_axi_intf_data {
'signals' => [ 'signals' => [
{ 'n' => 'WVALID', 'w' => '1', 's' => 'Manager', 'd' => 'Valid indicator' }, { 'n' => 'WVALID', 'w' => '1', 's' => 'Manager', 'd' => 'Valid indicator' },
{ 'n' => 'WREADY', 'w' => '1', 's' => 'Subordinate', 'd' => 'Ready indicator' }, { 'n' => 'WREADY', 'w' => '1', 's' => 'Subordinate', 'd' => 'Ready indicator' },
{ 'n' => 'WID','w' => 'ID_W_WIDTH','s' => 'Manager','d' => 'Transaction identifier for the write channels' },
{ 'n' => 'WDATA', 'w' => 'DATA_WIDTH', 's' => 'Manager', 'd' => 'Write data' }, { 'n' => 'WDATA', 'w' => 'DATA_WIDTH', 's' => 'Manager', 'd' => 'Write data' },
{ 'n' => 'WSTRB', 'w' => 'DATA_WIDTH_DIV_8', 's' => 'Manager', 'd' => 'Write data strobes' }, { 'n' => 'WSTRB', 'w' => 'DATA_WIDTH_DIV_8', 's' => 'Manager', 'd' => 'Write data strobes' },
{ 'n' => 'WTAG', 'w' => 'CEIL_DATA_WIDTH_DIV_128_TMS_4', 's' => 'Manager', 'd' => 'Memory Tag' }, { 'n' => 'WTAG', 'w' => 'CEIL_DATA_WIDTH_DIV_128_TMS_4', 's' => 'Manager', 'd' => 'Memory Tag' },

1
tb/verilator_trace_workaround.svh
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@@ -49,6 +49,7 @@
// A2.1.1 Write request channel // A2.1.1 Write request channel
always @(a_if.WVALID) t_if.WVALID <= a_if.WVALID; always @(a_if.WVALID) t_if.WVALID <= a_if.WVALID;
always @(a_if.WREADY) t_if.WREADY <= a_if.WREADY; always @(a_if.WREADY) t_if.WREADY <= a_if.WREADY;
always @(a_if.WID) t_if.WID <= a_if.WID;
always @(a_if.WDATA) t_if.WDATA <= a_if.WDATA; always @(a_if.WDATA) t_if.WDATA <= a_if.WDATA;
always @(a_if.WSTRB) t_if.WSTRB <= a_if.WSTRB; always @(a_if.WSTRB) t_if.WSTRB <= a_if.WSTRB;
always @(a_if.WTAG) t_if.WTAG <= a_if.WTAG; always @(a_if.WTAG) t_if.WTAG <= a_if.WTAG;