31 lines
702 B
Systemverilog
31 lines
702 B
Systemverilog
// Testbench interface for UVM-based verification environment
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interface testbench_if (
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output clk,
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output rst_n
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);
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logic clk_w;
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logic rst_n_w;
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assign clk = clk_w;
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assign rst_n = rst_n_w;
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// --------------------------------------------------
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// Clock generation
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initial begin
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clk_w = 0; // Initialize clock to 0 at time 0
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forever begin
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#5ns clk_w = ~clk_w; // Toggle clock every 5 ns
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end
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end
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// --------------------------------------------------
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// Initial reset
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initial begin
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rst_n_w = 0;
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repeat(20) @(posedge clk_w);
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rst_n_w = 1; // Release reset after 20 clocks
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end
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endinterface
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