31 lines
1.2 KiB
Systemverilog
31 lines
1.2 KiB
Systemverilog
// Testbench top module for UVM-based verification environment
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import uvm_pkg::*;
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module tb_top (input logic sys_clk);
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logic clk;
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logic rst_n;
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// Testbench interface to controll clocks, reset, etc.
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testbench_if tb_if(.clk(clk), .rst_n(rst_n));
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// AXI interface for manager and subordinate
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`AXI_INTF a_if (.ACLK(clk), .ARESETn(rst_n));
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// --------------------------------------------------
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initial begin
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uvm_config_db#(virtual `AXI_INTF.MANAGER)::set(uvm_root::get(), "uvm_test_top.env.axi_m", "axi_dvr_vif", a_if.MANAGER);
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uvm_config_db#(virtual `AXI_INTF.SUBORDINATE)::set(uvm_root::get(), "uvm_test_top.env.axi_s", "axi_dvr_vif", a_if.SUBORDINATE);
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uvm_config_db#(virtual `AXI_INTF)::set(uvm_root::get(), "uvm_test_top.env", "axi_mon_vif", a_if);
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uvm_config_db#(virtual testbench_if)::set(uvm_root::get(), "uvm_test_top.env", "tb_vif", tb_if);
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run_test();
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end
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// --------------------------------------------------
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initial begin
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$dumpfile("wave.vcd");
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$dumpvars(0, "tb_top");
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end
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`include "verilator_trace_workaround.svh"
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endmodule
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