800e9c40080d1b4fc1b2bdb51e20b5f605e8a25a
* Bare skeleton implementation of everything * Testbench builds with Verilator * Test runs
AXI Protocol Playground
Introduction
- There is no RTL design here. Just validation components working as both MANAGER and SUBORDINATE parts
Dependencies
- Verilator simulator
- UVM that works with Verilator
$ cd $UVM_HOME
$ git remote -v
origin https://github.com/antmicro/uvm-verilator.git (fetch)
origin https://github.com/antmicro/uvm-verilator.git (push)
$ git branch
current-patches
* current-patches-2
Description
Languages
SystemVerilog
75.7%
Perl
21%
Makefile
3.1%
Shell
0.2%