Mahesh Asolkar
800e9c4008
* Bare skeleton implementation of everything * Testbench builds with Verilator * Test runs
44 lines
1.4 KiB
Systemverilog
44 lines
1.4 KiB
Systemverilog
// ----------------------------------------------------------------------
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class axi_transaction extends uvm_sequence_item;
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// Declare AXI transaction fields
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rand axi_transaction_type_t txn_type; // Transaction type (read/write)
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rand bit [31:0] addr; // Address
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rand bit [31:0] data; // Data
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rand bit [3:0] strb; // Byte enable
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`uvm_object_utils_begin(axi_transaction)
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`uvm_field_enum(axi_transaction_type_t, txn_type, UVM_DEFAULT)
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`uvm_field_int(addr, UVM_DEFAULT)
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`uvm_field_int(data, UVM_DEFAULT)
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`uvm_field_int(strb, UVM_DEFAULT)
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`uvm_object_utils_end
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// Constructor
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function new(string name = "axi_transaction");
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super.new(name);
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endfunction
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// Copy method for cloning
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virtual function uvm_object clone();
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axi_transaction copy;
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copy = axi_transaction::type_id::create(get_name());
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copy.txn_type = this.txn_type;
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copy.addr = this.addr;
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copy.data = this.data;
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copy.strb = this.strb;
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return copy;
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endfunction
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// Comparison method for checking equality
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virtual function bit compare(uvm_object rhs);
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axi_transaction other;
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if (!$cast(other, rhs)) return 0; // Ensure type match
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return (this.txn_type == other.txn_type) &&
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(this.addr == other.addr) &&
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(this.data == other.data) &&
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(this.strb == other.strb);
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endfunction
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endclass : axi_transaction
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