Mahesh Asolkar
800e9c4008
* Bare skeleton implementation of everything * Testbench builds with Verilator * Test runs
40 lines
1.9 KiB
Systemverilog
40 lines
1.9 KiB
Systemverilog
// ----------------------------------------------------------------------
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// Tesbench defines
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// ----------------------------------------------------------------------
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// List of AXI parameters used in this testbench
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`define ADDR_WIDTH 32
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// `define ARSNOOP_WIDTH 1
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// `define AWCMO_WIDTH 1
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// `define AWSNOOP_WIDTH 1
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// `define BRESP_WIDTH 1
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`define CEIL_DATA_WIDTH_DIV_128 1
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`define CEIL_DATA_WIDTH_DIV_128_TMS_4 4
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`define CEIL_DATA_WIDTH_DIV_64 1
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`define DATA_WIDTH 64
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`define DATA_WIDTH_DIV_8 8
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// `define ID_R_WIDTH 1
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// `define ID_W_WIDTH 1
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// `define LOOP_R_WIDTH 1
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// `define LOOP_W_WIDTH 1
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// `define MECID_WIDTH 1
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// `define MPAM_WIDTH 1
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// `define RCHUNKNUM_WIDTH 1
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// `define RCHUNKSTRB_WIDTH 1
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// `define RRESP_WIDTH 1
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// `define SECSID_WIDTH 1
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// `define SID_WIDTH 1
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// `define SSID_WIDTH 1
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// `define SUBSYSID_WIDTH 1
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// `define SUM_USER_DATA_WIDTH_USER_RESP_WIDTH 1
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// `define USER_DATA_WIDTH 1
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// `define USER_REQ_WIDTH 1
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// `define USER_RESP_WIDTH 1
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// Defines
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`define AXI_INTF axi_intf #(.ADDR_WIDTH(`ADDR_WIDTH), \
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.CEIL_DATA_WIDTH_DIV_128(`CEIL_DATA_WIDTH_DIV_128), \
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.CEIL_DATA_WIDTH_DIV_128_TMS_4(`CEIL_DATA_WIDTH_DIV_128_TMS_4), \
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.CEIL_DATA_WIDTH_DIV_64(`CEIL_DATA_WIDTH_DIV_64), \
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.DATA_WIDTH(`DATA_WIDTH), \
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.DATA_WIDTH_DIV_8(`DATA_WIDTH_DIV_8))
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