Mahesh Asolkar
800e9c4008
* Bare skeleton implementation of everything * Testbench builds with Verilator * Test runs
26 lines
483 B
Systemverilog
26 lines
483 B
Systemverilog
`include "tb_params.sv"
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`include "tb_intf.sv"
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package tb_pkg;
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import uvm_pkg::*;
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import tb_types::*;
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`include "uvm_macros.svh"
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// Testbench defines
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// UVM data items
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`include "axi_transaction.sv"
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// UVM components
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`include "axi_driver.sv"
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`include "axi_monitor.sv"
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`include "axi_agent.sv"
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`include "tb_env.sv"
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// UVM sequences
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`include "tb_seq_base.sv"
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// Tests
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`include "test_base.sv"
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endpackage
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`include "tb_top.sv"
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