Mahesh Asolkar
800e9c4008
* Bare skeleton implementation of everything * Testbench builds with Verilator * Test runs
50 lines
1.4 KiB
Systemverilog
50 lines
1.4 KiB
Systemverilog
// Testbench top module for UVM-based verification environment
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import uvm_pkg::*;
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module tb_top (input logic sys_clk);
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logic clk;
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logic rst_n;
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// AXI interface for manager and subordinate
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`AXI_INTF a_if (.ACLK(clk), .ARESETn(rst_n));
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// // Instantiate the UVM testbench interface
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// testbench_if tb_if (
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// .clk(clk),
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// .m_if(m_if),
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// .s_if(s_if)
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// );
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// assign tb_if.rst_n = rst_n;
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// --------------------------------------------------
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initial begin
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uvm_config_db#(virtual `AXI_INTF.MANAGER)::set(uvm_root::get(), "uvm_test_top.env.axi_m", "axi_dvr_vif", a_if.MANAGER);
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uvm_config_db#(virtual `AXI_INTF.SUBORDINATE)::set(uvm_root::get(), "uvm_test_top.env.axi_s", "axi_dvr_vif", a_if.SUBORDINATE);
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run_test();
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end
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// --------------------------------------------------
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initial begin
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$dumpfile("wave.vcd");
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$dumpvars();
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end
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// --------------------------------------------------
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// Clock generation
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// TODO: Move to interface. Parameterize frequency
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initial begin
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clk = 0; // Initialize clock to 0 at time 0
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forever begin
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#5ns clk = ~clk; // Toggle clock every 5 ns
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end
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end
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// --------------------------------------------------
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initial begin
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rst_n = 0;
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#20ns rst_n = 1; // Release reset after 20 ns
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end
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endmodule
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