sample_uvm_tb/interfaces.sv

// -----
//
// Copyright (c) 2024 Mahesh Asolkar
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of
// this software and associated documentation files (the "Software"), to deal in
// the Software without restriction, including without limitation the rights to
// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is furnished to do
// so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
// -----
// Design and Testbench interfaces
interface design_if (
    input clk);

    logic        rst_n;
    logic [31:0] data_in;
    logic [31:0] data_out;

    modport DN (output data_out,      input  rst_n, clk, data_in);
    modport TB (input  clk, data_out, output rst_n, data_in);

    // ------------------------------------------------------------
    initial begin : trk
        string trk_name;
        integer trk_h;

        trk_name = $sformatf("%m.out");
        trk_h = $fopen(trk_name, "w");

        $fdisplay(trk_h,  "Tracker: %s", trk_name);
        $display("Starting tracker: %s", trk_name);

        forever begin
            @(clk or rst_n or data_in or data_out);
            $fmonitor(trk_h, "@%6t: %b %b %h %h", $time,
                rst_n, clk, data_in, data_out);
        end
    end
endinterface

// ----------------------------------------------------------------------
interface testbench_if (
    input clk,
    virtual design_if d1_if,
    virtual design_if d2_if);

    logic rst_n;

    modport DN (input  rst_n, clk);
    modport TB (input  clk, output rst_n);
endinterface