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Moved tracker code from design to interface

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This commit is contained in:
Mahesh Asolkar
2024-12-26 22:15:31 -08:00
parent e4e8457f95
commit caffc337c3
2 changed files with 68 additions and 18 deletions
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44
design.sv
View File

@@ -1,40 +1,48 @@
// -----
//
// Copyright (c) 2024 Mahesh Asolkar
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of
// this software and associated documentation files (the "Software"), to deal in
// the Software without restriction, including without limitation the rights to
// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is furnished to do
// so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
// -----
// Some simple design
module rtl_design(design_if intf);
logic [31:0] data_out_drv = 0;
assign intf.data_out = data_out_drv;
string trk_name;
integer trk_h;
// ------------------------------------------------------------
initial begin
data_out_drv = 32'h0;
end
// ------------------------------------------------------------
always @(posedge intf.clk) begin
if (intf.rst_n) begin
data_out_drv = intf.data_in;
end
end
// ------------------------------------------------------------
always_latch @(intf.rst_n) begin
if (!intf.rst_n) begin
data_out_drv = 32'h0;
end
end
initial begin
trk_name = $sformatf("%m.out");
trk_h = $fopen(trk_name, "w");
$fdisplay(trk_h, "Tracker: %s", trk_name);
$display("Starting tracker: %s", trk_name);
$fmonitor(trk_h, "@%6t: %b %b %h %h", $time,
intf.rst_n, intf.clk, intf.data_in, intf.data_out);
end
function void be_done();
$display("Closing tracker %s", trk_name);
$fclose(trk_h);
endfunction
endmodule

42
interfaces.sv
View File

@@ -1,3 +1,26 @@
// -----
//
// Copyright (c) 2024 Mahesh Asolkar
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of
// this software and associated documentation files (the "Software"), to deal in
// the Software without restriction, including without limitation the rights to
// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is furnished to do
// so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
// -----
// Design and Testbench interfaces
interface design_if (
input clk);
@@ -8,8 +31,27 @@ interface design_if (
modport DN (output data_out, input rst_n, clk, data_in);
modport TB (input clk, data_out, output rst_n, data_in);
// ------------------------------------------------------------
initial begin : trk
string trk_name;
integer trk_h;
trk_name = $sformatf("%m.out");
trk_h = $fopen(trk_name, "w");
$fdisplay(trk_h, "Tracker: %s", trk_name);
$display("Starting tracker: %s", trk_name);
forever begin
@(clk or rst_n or data_in or data_out);
$fmonitor(trk_h, "@%6t: %b %b %h %h", $time,
rst_n, clk, data_in, data_out);
end
end
endinterface
// ----------------------------------------------------------------------
interface testbench_if (
input clk,
virtual design_if d1_if,