Added license info

This commit is contained in:
2024-12-26 22:15:54 -08:00
parent caffc337c3
commit 3a0c88205d
9 changed files with 278 additions and 6 deletions

View File

@@ -1,10 +1,43 @@
# -----
#
# Copyright (c) 2024 Mahesh Asolkar
#
# Permission is hereby granted, free of charge, to any person obtaining a copy of
# this software and associated documentation files (the "Software"), to deal in
# the Software without restriction, including without limitation the rights to
# use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
# of the Software, and to permit persons to whom the Software is furnished to do
# so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
# copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# -----
# Make and run project
UVM_HOME=/home/mahesh/git/uvm-verilator
PROJ=uvm_tb
SV_OUT=obj_dir/Vuvm_pkg__verFiles.dat
SV_BUILD_LOG=$(PROJ)_build_sv.log
CPP_OUT=$(PROJ).sim
CPP_BUILD_LOG=$(PROJ)_build_cpp.log
SIM_LOG=$(PROJ)_sim.log
SV_FILES=$(shell ls *.sv)
SV_SRC=$(UVM_HOME)/src/uvm_pkg.sv tb_pkg.sv
DPI_SRC=$(UVM_HOME)/src/dpi/uvm_dpi.cc
DPI_INC=-I/usr/share/verilator/include
SV_DEPS=$(SV_FILES)
CPP_SRC=sim_$(PROJ).cpp
@@ -19,13 +52,11 @@ DISABLED_WARNINGS=-Wno-WIDTHTRUNC -Wno-WIDTHEXPAND \
-Wno-SYMRSVDWORD -Wno-CASEINCOMPLETE
ifndef TEST_NAME
TEST_NAME=test_base
TEST_NAME=test_basic
endif
build: $(SV_DEPS)
verilator -I$(UVM_HOME)/src -I. \
BUILD_ARGS=-I$(UVM_HOME)/src -I. \
-o $(PROJ).sim \
--binary \
-j 4 \
--error-limit 10 \
--timing $(TIMESCALE) \
@@ -34,9 +65,25 @@ build: $(SV_DEPS)
$(DISABLED_WARNINGS) \
$(SV_SRC)
run:
build: build_sv build_cpp
echo "Build done"
build_sv: $(SV_OUT)
$(SV_OUT): $(SV_DEPS)
verilator --cc $(BUILD_ARGS) >& $(SV_BUILD_LOG)
build_cpp: $(CPP_OUT)
$(CPP_OUT): $(SV_OUT)
verilator --binary $(BUILD_ARGS) >& $(CPP_BUILD_LOG)
lint:
verilator --lint-only $(BUILD_ARGS)
run: $(CPP_OUT)
if [ ! -d logs/$(TEST_NAME) ]; then mkdir -p logs/$(TEST_NAME); fi
cd logs/$(TEST_NAME) && ../../obj_dir/$(PROJ).sim +UVM_TESTNAME=$(TEST_NAME) |& tee sim.log
cd logs/$(TEST_NAME) && ../../obj_dir/$(PROJ).sim +UVM_TESTNAME=$(TEST_NAME) |& tee $(SIM_LOG)
clean:
rm -rf obj_dir