Added license info

.gitignore

@@ -1,2 +1,25 @@
+# -----
+#
+# Copyright (c) 2024 Mahesh Asolkar
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy of
+# this software and associated documentation files (the "Software"), to deal in
+# the Software without restriction, including without limitation the rights to
+# use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+# of the Software, and to permit persons to whom the Software is furnished to do
+# so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in all
+# copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# -----
 logs
 obj_dir

Makefile

@@ -1,10 +1,43 @@
+# -----
+#
+# Copyright (c) 2024 Mahesh Asolkar
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy of
+# this software and associated documentation files (the "Software"), to deal in
+# the Software without restriction, including without limitation the rights to
+# use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+# of the Software, and to permit persons to whom the Software is furnished to do
+# so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in all
+# copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# -----
 # Make and run project
 UVM_HOME=/home/mahesh/git/uvm-verilator
 
 PROJ=uvm_tb
 
+SV_OUT=obj_dir/Vuvm_pkg__verFiles.dat
+SV_BUILD_LOG=$(PROJ)_build_sv.log
+
+CPP_OUT=$(PROJ).sim
+CPP_BUILD_LOG=$(PROJ)_build_cpp.log
+
+SIM_LOG=$(PROJ)_sim.log
+
 SV_FILES=$(shell ls *.sv)
 SV_SRC=$(UVM_HOME)/src/uvm_pkg.sv tb_pkg.sv
+DPI_SRC=$(UVM_HOME)/src/dpi/uvm_dpi.cc
+DPI_INC=-I/usr/share/verilator/include
 SV_DEPS=$(SV_FILES)
 
 CPP_SRC=sim_$(PROJ).cpp
@@ -19,13 +52,11 @@ DISABLED_WARNINGS=-Wno-WIDTHTRUNC -Wno-WIDTHEXPAND \
                   -Wno-SYMRSVDWORD -Wno-CASEINCOMPLETE
 
 ifndef TEST_NAME
-    TEST_NAME=test_base
+    TEST_NAME=test_basic
 endif
 
-build: $(SV_DEPS)
+BUILD_ARGS=-I$(UVM_HOME)/src -I. \
-	verilator -I$(UVM_HOME)/src -I. \
         -o $(PROJ).sim \
-        --binary \
         -j 4 \
         --error-limit 10 \
         --timing $(TIMESCALE) \
@@ -34,9 +65,25 @@ build: $(SV_DEPS)
         $(DISABLED_WARNINGS) \
         $(SV_SRC)
 
-run:
+build: build_sv build_cpp
+	echo "Build done"
+
+build_sv: $(SV_OUT)
+
+$(SV_OUT): $(SV_DEPS)
+	verilator --cc $(BUILD_ARGS) >& $(SV_BUILD_LOG)
+
+build_cpp: $(CPP_OUT)
+
+$(CPP_OUT): $(SV_OUT)
+	verilator --binary $(BUILD_ARGS) >& $(CPP_BUILD_LOG)
+
+lint:
+	verilator --lint-only $(BUILD_ARGS)
+
+run: $(CPP_OUT)
 	if [ ! -d logs/$(TEST_NAME) ]; then mkdir -p logs/$(TEST_NAME); fi
-	cd logs/$(TEST_NAME) && ../../obj_dir/$(PROJ).sim +UVM_TESTNAME=$(TEST_NAME) |& tee sim.log
+	cd logs/$(TEST_NAME) && ../../obj_dir/$(PROJ).sim +UVM_TESTNAME=$(TEST_NAME) |& tee $(SIM_LOG)
 
 clean:
 	rm -rf obj_dir

agent_reset.sv

@@ -1,20 +1,47 @@
+// -----
+//
+// Copyright (c) 2024 Mahesh Asolkar
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of
+// this software and associated documentation files (the "Software"), to deal in
+// the Software without restriction, including without limitation the rights to
+// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+// of the Software, and to permit persons to whom the Software is furnished to do
+// so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+// -----
 class sequencer_reset extends uvm_sequencer;
     `uvm_component_utils(sequencer_reset)
 
+    // ------------------------------------------------------------
     function new(string name, uvm_component parent);
         super.new(name, parent);
     endfunction
 endclass
 
+// ----------------------------------------------------------------------
 class driver_reset extends uvm_driver;
     virtual testbench_if tb_if;
 
     `uvm_component_utils(driver_reset)
 
+    // ------------------------------------------------------------
     function new(string name, uvm_component parent);
         super.new(name, parent);
     endfunction
 
+    // ------------------------------------------------------------
     function void build_phase(uvm_phase phase);
         super.build_phase(phase);
 
@@ -23,6 +50,7 @@ class driver_reset extends uvm_driver;
         end
     endfunction
 
+    // ------------------------------------------------------------
     virtual task run_phase(uvm_phase phase);
         forever begin
             @(posedge tb_if.rst_n);
@@ -34,6 +62,7 @@ class driver_reset extends uvm_driver;
         end
     endtask
 
+    // ------------------------------------------------------------
     task drive_item(uvm_sequence_item req);
         `uvm_info("drive_item", $sformatf("Initiating reset..."), UVM_LOW)
         tb_if.rst_n = 0;
@@ -43,15 +72,18 @@ class driver_reset extends uvm_driver;
     endtask
 endclass
 
+// ----------------------------------------------------------------------
 class monitor_reset extends uvm_monitor;
     virtual testbench_if tb_if;
 
     `uvm_component_utils(monitor_reset)
 
+    // ------------------------------------------------------------
     function new(string name, uvm_component parent);
         super.new(name, parent);
     endfunction
 
+    // ------------------------------------------------------------
     function void build_phase(uvm_phase phase);
         super.build_phase(phase);
 
@@ -60,12 +92,14 @@ class monitor_reset extends uvm_monitor;
         end
     endfunction
 
+    // ------------------------------------------------------------
     virtual task run_phase(uvm_phase phase);
         fork
             do_monitor();
         join
     endtask
 
+    // ------------------------------------------------------------
     task do_monitor();
         bit prev_val;
 
@@ -91,6 +125,7 @@ class monitor_reset extends uvm_monitor;
     endtask
 endclass
 
+// ----------------------------------------------------------------------
 class agent_reset extends uvm_agent;
     sequencer_reset sequencer;
     driver_reset    driver;
@@ -98,10 +133,12 @@ class agent_reset extends uvm_agent;
 
     `uvm_component_utils(agent_reset)
 
+    // ------------------------------------------------------------
     function new(string name, uvm_component parent);
         super.new(name, parent);
     endfunction
 
+    // ------------------------------------------------------------
     function void build_phase(uvm_phase phase);
         super.build_phase(phase);
 
@@ -112,6 +149,7 @@ class agent_reset extends uvm_agent;
         `uvm_info("build_phase", $sformatf("Building done"), UVM_LOW)
     endfunction
 
+    // ------------------------------------------------------------
     function void connect_phase(uvm_phase phase);
         super.connect_phase(phase);
 

agent_tb.sv

@@ -1,6 +1,30 @@
+// -----
+//
+// Copyright (c) 2024 Mahesh Asolkar
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of
+// this software and associated documentation files (the "Software"), to deal in
+// the Software without restriction, including without limitation the rights to
+// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+// of the Software, and to permit persons to whom the Software is furnished to do
+// so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+// -----
 class sequencer_tb extends uvm_sequencer;
     `uvm_component_utils(sequencer_tb)
 
+    // ------------------------------------------------------------
     function new(string name, uvm_component parent);
         super.new(name, parent);
     endfunction

seq_basic.sv

@@ -1,28 +1,57 @@
+// -----
+//
+// Copyright (c) 2024 Mahesh Asolkar
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of
+// this software and associated documentation files (the "Software"), to deal in
+// the Software without restriction, including without limitation the rights to
+// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+// of the Software, and to permit persons to whom the Software is furnished to do
+// so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+// -----
 class seq_base extends uvm_sequence;
     testbench_env tb_env;
 
     `uvm_object_utils(seq_base)
 
+    // ------------------------------------------------------------
     function new(string name = "seq_base");
         super.new(name);
     endfunction
 
+    // ------------------------------------------------------------
     function void set_handles(testbench_env env);
         tb_env = env;
     endfunction
 
+    // ------------------------------------------------------------
     virtual task body();
         bit ok = uvm_config_db#(testbench_env)::get(m_sequencer, "", "tb_env", tb_env);
     endtask
 endclass
 
+// ----------------------------------------------------------------------
 class seq_basic extends seq_base;
     `uvm_object_utils(seq_basic)
 
+    // ------------------------------------------------------------
     function new(string name = "seq_basic");
         super.new(name);
     endfunction
 
+    // ------------------------------------------------------------
     virtual task body();
         super.body();
 
@@ -38,6 +67,7 @@ class seq_basic extends seq_base;
         `uvm_info("body", $sformatf("Stimulus done."), UVM_LOW)
     endtask
 
+    // ------------------------------------------------------------
     task d_stimulus(virtual design_if d_if, int inst_n);
         `uvm_info("d_stimulus", $sformatf("Inst-%0d: Initiating stimulus...", inst_n), UVM_LOW);
         repeat(20) @(negedge tb_env.tb_if.clk);
@@ -51,13 +81,16 @@ class seq_basic extends seq_base;
     endtask
 endclass
 
+// ----------------------------------------------------------------------
 class seq_reset extends seq_base;
     `uvm_object_utils(seq_reset)
 
+    // ------------------------------------------------------------
     function new(string name = "seq_reset");
         super.new(name);
     endfunction
 
+    // ------------------------------------------------------------
     virtual task body();
         super.body();
 

tb_pkg.sv

@@ -1,3 +1,26 @@
+// -----
+//
+// Copyright (c) 2024 Mahesh Asolkar
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of
+// this software and associated documentation files (the "Software"), to deal in
+// the Software without restriction, including without limitation the rights to
+// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+// of the Software, and to permit persons to whom the Software is furnished to do
+// so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+// -----
 `include "interfaces.sv"
 `include "design.sv"
 package tb_pkg;

test_base.sv

@@ -1,13 +1,38 @@
+// -----
+//
+// Copyright (c) 2024 Mahesh Asolkar
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of
+// this software and associated documentation files (the "Software"), to deal in
+// the Software without restriction, including without limitation the rights to
+// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+// of the Software, and to permit persons to whom the Software is furnished to do
+// so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+// -----
 class test_base extends uvm_test;
     `uvm_component_utils(test_base)
 
     testbench_env tb_env;
     uvm_table_printer tb_printer;
 
+    // ------------------------------------------------------------
     function new(string name, uvm_component parent);
         super.new(name, parent);
     endfunction
 
+    // ------------------------------------------------------------
     function void build_phase(uvm_phase phase);
         super.build_phase(phase);
 
@@ -17,10 +42,12 @@ class test_base extends uvm_test;
         uvm_config_db#(testbench_env)::set(uvm_root::get(), "*", "tb_env", tb_env);
     endfunction
 
+    // ------------------------------------------------------------
     virtual function void end_of_elaboration_phase(uvm_phase phase);
         `uvm_info("end_of_elaboration_phase", $sformatf("Topology:\n%s", this.sprint(tb_printer)), UVM_LOW)
     endfunction
 
+    // ------------------------------------------------------------
     virtual task run_phase(uvm_phase phase);
         uvm_objection objection;
 
@@ -40,6 +67,7 @@ class test_base extends uvm_test;
         phase.drop_objection(this);
     endtask
 
+    // ------------------------------------------------------------
     virtual task run_reset_phase(uvm_phase phase);
         seq_reset rst_seq;
 
@@ -49,22 +77,27 @@ class test_base extends uvm_test;
         `uvm_info("run_reset_phase", $sformatf("Finishing reset"), UVM_LOW)
     endtask
 
+    // ------------------------------------------------------------
     virtual task run_test_phase(uvm_phase phase);
         `uvm_warning("run_test_phase", $sformatf("This content is expected to be implemented in specific tests"))
     endtask
 
+    // ------------------------------------------------------------
     virtual task run_flush_phase(uvm_phase phase);
         `uvm_info("run_flush_phase", $sformatf("Finishing test"), UVM_LOW)
     endtask
 endclass
 
+// ----------------------------------------------------------------------
 class test_basic extends test_base;
     `uvm_component_utils(test_basic)
 
+    // ------------------------------------------------------------
     function new(string name, uvm_component parent);
         super.new(name, parent);
     endfunction
 
+    // ------------------------------------------------------------
     virtual task run_test_phase(uvm_phase phase);
         seq_basic tst_seq;
 

testbench_env.sv

@@ -1,3 +1,26 @@
+// -----
+//
+// Copyright (c) 2024 Mahesh Asolkar
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of
+// this software and associated documentation files (the "Software"), to deal in
+// the Software without restriction, including without limitation the rights to
+// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+// of the Software, and to permit persons to whom the Software is furnished to do
+// so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+// -----
 // Top class
 class testbench_env extends uvm_component;
     string name;
@@ -8,11 +31,13 @@ class testbench_env extends uvm_component;
 
     `uvm_component_utils(testbench_env)
 
+    // ------------------------------------------------------------
     function new(string name, uvm_component parent);
         super.new(name, parent);
         `uvm_info("new", $sformatf("Initialized testbench %s", name), UVM_LOW)
     endfunction
 
+    // ------------------------------------------------------------
     function void build_phase(uvm_phase phase);
         super.build_phase(phase);
 
@@ -20,6 +45,7 @@ class testbench_env extends uvm_component;
         tb_sequencer  = sequencer_tb::type_id::create("tb_sequencer", this);
     endfunction
 
+    // ------------------------------------------------------------
     function void connect_phase(uvm_phase phase);
         super.connect_phase(phase);
 
@@ -30,10 +56,12 @@ class testbench_env extends uvm_component;
         `uvm_info("connect_phase", $sformatf("Build phase complete"), UVM_LOW)
     endfunction
 
+    // ------------------------------------------------------------
     function uvm_sequencer get_tb_sequencer();
         return tb_sequencer;
     endfunction
 
+    // ------------------------------------------------------------
     function uvm_sequencer get_rst_sequencer();
         return rst_agt.sequencer;
     endfunction

uvm_tb.sv

@@ -1,3 +1,26 @@
+// -----
+//
+// Copyright (c) 2024 Mahesh Asolkar
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of
+// this software and associated documentation files (the "Software"), to deal in
+// the Software without restriction, including without limitation the rights to
+// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+// of the Software, and to permit persons to whom the Software is furnished to do
+// so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+//
+// -----
 // uvm_tb in SystemVerilog
 import uvm_pkg::*;