Added more verilator and UVM specifics to README

README.md

@@ -1,5 +1,13 @@
 # Sample UVM testbench
 
-This is a simple testbench using UVM framework.
+This is a simple playground testbench. It is written in SystemVerilog using UVM framework.
 
-`Makefile` uses the Verilator simulator to build and run the testbench.
+`Makefile` uses the [Verilator](https://www.veripool.org/verilator/) simulator to build and run the testbench.
+
+## UVM for Verilator
+
+* This testbench uses UVM modified to work with Verilator. This comes from project maintained by good folks at [Antmicro](https://antmicro.com/).
+
+```shell
+    % git clone https://github.com/antmicro/uvm-verilator.git -b current-patches-2
+```