Initial commit

uvm_tb.sv

@@ -0,0 +1,55 @@
+// uvm_tb in SystemVerilog
+import uvm_pkg::*;
+
+module uvm_tb (input logic sys_clk);
+    logic clk;
+    logic rst_n;
+    logic [31:0] d1_data_i;
+    logic [31:0] d1_data_o;
+    logic [31:0] d2_data_i;
+    logic [31:0] d2_data_o;
+
+    design_if d1_if(.clk(clk));
+    assign d1_if.rst_n = rst_n;
+    assign d1_if.data_in = d1_data_i;
+    assign d1_data_o = d1_if.data_out;
+
+    design_if d2_if(.clk(clk));
+    assign d2_if.rst_n = rst_n;
+    assign d2_if.data_in = d2_data_i;
+    assign d2_data_o = d2_if.data_out;
+
+    testbench_if uvm_tb_if(
+        .clk(clk),
+        .d1_if(d1_if),
+        .d2_if(d2_if)
+    );
+    assign rst_n = uvm_tb_if.rst_n;
+
+    rtl_design d1(d1_if.DN);
+
+    rtl_design d2(d2_if.DN);
+
+    initial begin
+        // TbEnv t = new(.name("uvm_tbTbEnv"), .parent(null));
+        //               // .intf(uvm_tb_if.TB));
+
+        // t.set_handles(uvm_tb_if);
+        // // t.run_phase();
+
+        // $display("Simulation with UVM done at %t", $time);
+        // $finish;
+
+        uvm_config_db#(virtual testbench_if)::set(uvm_root::get(), "*", "tb_vif", uvm_tb_if);
+
+        run_test();
+    end
+
+    //  initial begin
+    //      $dumpfile("wave.vcd");
+    //      $dumpvars();
+    //  end
+
+    // TODO: Move to interface. Parameterize frequency
+    always #5 clk = ~clk;
+endmodule