Mahesh Asolkar e4e8457f95 Initial commit

2024-08-11 21:48:11 -07:00

.gitignore

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agent_reset.sv

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agent_tb.sv

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design.sv

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interfaces.sv

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Makefile

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seq_basic.sv

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tb_pkg.sv

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test_base.sv

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testbench_env.sv

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uvm_tb.sv

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Description

Sample UVM testbench

46 KiB

Languages

SystemVerilog 89.6%

Makefile 10.4%