General Makefile updates

Makefile

@@ -22,7 +22,7 @@
 #
 # -----
 # Make and run project
-UVM_HOME=/home/mahesh/git/uvm-verilator
+UVM_HOME=$(HOME)/git/uvm-verilator
 
 PROJ=uvm_tb
 
@@ -51,10 +51,6 @@ DISABLED_WARNINGS=-Wno-WIDTHTRUNC -Wno-WIDTHEXPAND \
                   -Wno-MISINDENT -Wno-REALCVT \
                   -Wno-SYMRSVDWORD -Wno-CASEINCOMPLETE
 
-ifndef TEST_NAME
-    TEST_NAME=test_basic
-endif
-
 BUILD_ARGS=-I$(UVM_HOME)/src -I. \
         -o $(PROJ).sim \
         -j 4 \
@@ -65,25 +61,48 @@ BUILD_ARGS=-I$(UVM_HOME)/src -I. \
         $(DISABLED_WARNINGS) \
         $(SV_SRC)
 
+ifndef TEST_NAME
+    TEST_NAME=test_basic
+endif
+
+#
+# Full build to generate testbench executable (Default target)
+#
 build: build_sv build_cpp
 	echo "Build done"
 
+#
+# C code generation from SystemVerilog
+#
 build_sv: $(SV_OUT)
 
 $(SV_OUT): $(SV_DEPS)
 	verilator --cc $(BUILD_ARGS) >& $(SV_BUILD_LOG)
 
+#
+# C code build to generate testbench executable
+#
 build_cpp: $(CPP_OUT)
 
 $(CPP_OUT): $(SV_OUT)
 	verilator --binary $(BUILD_ARGS) >& $(CPP_BUILD_LOG)
 
+#
+# Run just lint to detect syntax errors during development
+#
 lint:
 	verilator --lint-only $(BUILD_ARGS)
 
+#
+# Run test. Use TEST_NAME=<test name> on make line to pick the test
+#
 run: $(CPP_OUT)
 	if [ ! -d logs/$(TEST_NAME) ]; then mkdir -p logs/$(TEST_NAME); fi
 	cd logs/$(TEST_NAME) && ../../obj_dir/$(PROJ).sim +UVM_TESTNAME=$(TEST_NAME) |& tee $(SIM_LOG)
 
+#
+# Remove generated files
+# - This will not remove 'logs' directory that contains simulation logs
+#
 clean:
-	rm -rf obj_dir
+	rm -rf obj_dir $(PROJ)*.log