109 lines
3.0 KiB
Makefile
109 lines
3.0 KiB
Makefile
# -----
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#
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# Copyright (c) 2024 Mahesh Asolkar
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy of
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# this software and associated documentation files (the "Software"), to deal in
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# the Software without restriction, including without limitation the rights to
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# use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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# of the Software, and to permit persons to whom the Software is furnished to do
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# so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in all
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# copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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# SOFTWARE.
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#
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# -----
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# Make and run project
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UVM_HOME=$(HOME)/git/uvm-verilator
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PROJ=uvm_tb
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SV_OUT=obj_dir/Vuvm_pkg__verFiles.dat
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SV_BUILD_LOG=$(PROJ)_build_sv.log
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CPP_OUT=$(PROJ).sim
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CPP_BUILD_LOG=$(PROJ)_build_cpp.log
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SIM_LOG=$(PROJ)_sim.log
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SV_FILES=$(shell ls *.sv)
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SV_SRC=$(UVM_HOME)/src/uvm_pkg.sv tb_pkg.sv
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DPI_SRC=$(UVM_HOME)/src/dpi/uvm_dpi.cc
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DPI_INC=-I/usr/share/verilator/include
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SV_DEPS=$(SV_FILES)
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CPP_SRC=sim_$(PROJ).cpp
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TIMESCALE= --timescale '1ns/1ns'
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UVM_DEFINES=+define+UVM_NO_DPI \
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+define+UVM_REPORT_DISABLE_FILE_LINE
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DISABLED_WARNINGS=-Wno-WIDTHTRUNC -Wno-WIDTHEXPAND \
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-Wno-CASTCONST -Wno-CONSTRAINTIGN \
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-Wno-MISINDENT -Wno-REALCVT \
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-Wno-SYMRSVDWORD -Wno-CASEINCOMPLETE
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BUILD_ARGS=-I$(UVM_HOME)/src -I. \
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-o $(PROJ).sim \
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-j 4 \
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--error-limit 10 \
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--timing $(TIMESCALE) \
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+define+SVA_ON \
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$(UVM_DEFINES) \
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$(DISABLED_WARNINGS) \
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$(SV_SRC)
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ifndef TEST_NAME
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TEST_NAME=test_basic
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endif
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#
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# Full build to generate testbench executable (Default target)
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#
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build: build_sv build_cpp
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echo "Build done"
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#
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# C code generation from SystemVerilog
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#
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build_sv: $(SV_OUT)
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$(SV_OUT): $(SV_DEPS)
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verilator --cc $(BUILD_ARGS) >& $(SV_BUILD_LOG)
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#
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# C code build to generate testbench executable
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#
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build_cpp: $(CPP_OUT)
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$(CPP_OUT): $(SV_OUT)
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verilator --binary $(BUILD_ARGS) >& $(CPP_BUILD_LOG)
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#
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# Run just lint to detect syntax errors during development
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#
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lint:
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verilator --lint-only $(BUILD_ARGS)
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#
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# Run test. Use TEST_NAME=<test name> on make line to pick the test
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#
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run: $(CPP_OUT)
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if [ ! -d logs/$(TEST_NAME) ]; then mkdir -p logs/$(TEST_NAME); fi
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cd logs/$(TEST_NAME) && ../../obj_dir/$(PROJ).sim +UVM_TESTNAME=$(TEST_NAME) |& tee $(SIM_LOG)
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#
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# Remove generated files
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# - This will not remove 'logs' directory that contains simulation logs
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#
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clean:
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rm -rf obj_dir $(PROJ)*.log
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