66 lines
2.2 KiB
Systemverilog
66 lines
2.2 KiB
Systemverilog
// -----
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//
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// Copyright (c) 2024 Mahesh Asolkar
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of
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// this software and associated documentation files (the "Software"), to deal in
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// the Software without restriction, including without limitation the rights to
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// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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// of the Software, and to permit persons to whom the Software is furnished to do
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// so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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//
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// -----
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// Design and Testbench interfaces
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interface design_if (
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input clk);
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logic rst_n;
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logic [31:0] data_in;
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logic [31:0] data_out;
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modport DN (output data_out, input rst_n, clk, data_in);
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modport TB (input clk, data_out, output rst_n, data_in);
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// ------------------------------------------------------------
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initial begin : trk
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string trk_name;
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integer trk_h;
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trk_name = $sformatf("%m.out");
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trk_h = $fopen(trk_name, "w");
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$fdisplay(trk_h, "Tracker: %s", trk_name);
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$display("Starting tracker: %s", trk_name);
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forever begin
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@(clk or rst_n or data_in or data_out);
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$fmonitor(trk_h, "@%6t: %b %b %h %h", $time,
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rst_n, clk, data_in, data_out);
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end
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end
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endinterface
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// ----------------------------------------------------------------------
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interface testbench_if (
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input clk,
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virtual design_if d1_if,
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virtual design_if d2_if);
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logic rst_n;
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modport DN (input rst_n, clk);
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modport TB (input clk, output rst_n);
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endinterface
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