18 lines
314 B
Systemverilog
18 lines
314 B
Systemverilog
`include "interfaces.sv"
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`include "design.sv"
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package tb_pkg;
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import uvm_pkg::*;
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// Environment
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`include "agent_reset.sv"
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`include "agent_tb.sv"
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`include "testbench_env.sv"
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// Sequences
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`include "seq_basic.sv"
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// Tests
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`include "test_base.sv"
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endpackage
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`include "uvm_tb.sv"
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