41 lines
1.2 KiB
Systemverilog
41 lines
1.2 KiB
Systemverilog
// Top class
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class testbench_env extends uvm_component;
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string name;
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virtual testbench_if tb_if;
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agent_reset rst_agt;
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sequencer_tb tb_sequencer;
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`uvm_component_utils(testbench_env)
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function new(string name, uvm_component parent);
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super.new(name, parent);
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`uvm_info("new", $sformatf("Initialized testbench %s", name), UVM_LOW)
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endfunction
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function void build_phase(uvm_phase phase);
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super.build_phase(phase);
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rst_agt = agent_reset::type_id::create("reset_agent", this);
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tb_sequencer = sequencer_tb::type_id::create("tb_sequencer", this);
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endfunction
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function void connect_phase(uvm_phase phase);
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super.connect_phase(phase);
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if (!uvm_config_db#(virtual testbench_if)::get(this, "", "tb_vif", tb_if)) begin
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`uvm_fatal("CFG_DB_FAIL", $sformatf("Failed to fetch interface for %0s", get_full_name()))
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end
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`uvm_info("connect_phase", $sformatf("Build phase complete"), UVM_LOW)
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endfunction
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function uvm_sequencer get_tb_sequencer();
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return tb_sequencer;
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endfunction
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function uvm_sequencer get_rst_sequencer();
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return rst_agt.sequencer;
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endfunction
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endclass
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