Mahesh Asolkar
800e9c4008
* Bare skeleton implementation of everything * Testbench builds with Verilator * Test runs
22 lines
436 B
Markdown
22 lines
436 B
Markdown
# AXI Protocol Playground
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## Introduction
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* There is no RTL design here. Just validation components working as both
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MANAGER and SUBORDINATE parts
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## Dependencies
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* Verilator simulator
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* UVM that works with Verilator
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```
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$ cd $UVM_HOME
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$ git remote -v
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origin https://github.com/antmicro/uvm-verilator.git (fetch)
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origin https://github.com/antmicro/uvm-verilator.git (push)
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$ git branch
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current-patches
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* current-patches-2
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```
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