Mahesh Asolkar
800e9c4008
* Bare skeleton implementation of everything * Testbench builds with Verilator * Test runs
27 lines
1.0 KiB
Systemverilog
27 lines
1.0 KiB
Systemverilog
// Testbench interface for UVM-based verification environment
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interface testbench_if (
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input clk,
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virtual axi_intf #(.ADDR_WIDTH(`ADDR_WIDTH),
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.CEIL_DATA_WIDTH_DIV_128(`CEIL_DATA_WIDTH_DIV_128),
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.CEIL_DATA_WIDTH_DIV_128_TMS_4(`CEIL_DATA_WIDTH_DIV_128_TMS_4),
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.CEIL_DATA_WIDTH_DIV_64(`CEIL_DATA_WIDTH_DIV_64),
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.DATA_WIDTH(`DATA_WIDTH),
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.DATA_WIDTH_DIV_8(`DATA_WIDTH_DIV_8)) m_if,
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virtual axi_intf #(.ADDR_WIDTH(`ADDR_WIDTH),
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.CEIL_DATA_WIDTH_DIV_128(`CEIL_DATA_WIDTH_DIV_128),
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.CEIL_DATA_WIDTH_DIV_128_TMS_4(`CEIL_DATA_WIDTH_DIV_128_TMS_4),
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.CEIL_DATA_WIDTH_DIV_64(`CEIL_DATA_WIDTH_DIV_64),
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.DATA_WIDTH(`DATA_WIDTH),
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.DATA_WIDTH_DIV_8(`DATA_WIDTH_DIV_8)) s_if);
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logic rst_n;
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initial begin
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forever begin
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@(clk or rst_n);
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$monitor("@%6t: %b %b ", $time,
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rst_n, clk);
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end
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end
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endinterface
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