sample_uvm_tb/design.sv

// -----
//
// Copyright (c) 2024 Mahesh Asolkar
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of
// this software and associated documentation files (the "Software"), to deal in
// the Software without restriction, including without limitation the rights to
// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is furnished to do
// so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
// -----
// Some simple design
module rtl_design(design_if intf);

    logic [31:0] data_out_drv = 0;
    assign intf.data_out = data_out_drv;

    // ------------------------------------------------------------
    initial begin
        data_out_drv = 32'h0;
    end

    // ------------------------------------------------------------
    always @(posedge intf.clk) begin
        if (intf.rst_n) begin
            data_out_drv = intf.data_in;
        end
    end

    // ------------------------------------------------------------
    always_latch @(intf.rst_n) begin
        if (!intf.rst_n) begin
            data_out_drv = 32'h0;
        end
    end
endmodule