41 lines
941 B
Systemverilog
41 lines
941 B
Systemverilog
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// Some simple design
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module rtl_design(design_if intf);
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logic [31:0] data_out_drv = 0;
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assign intf.data_out = data_out_drv;
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string trk_name;
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integer trk_h;
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initial begin
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data_out_drv = 32'h0;
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end
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always @(posedge intf.clk) begin
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if (intf.rst_n) begin
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data_out_drv = intf.data_in;
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end
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end
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always_latch @(intf.rst_n) begin
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if (!intf.rst_n) begin
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data_out_drv = 32'h0;
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end
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end
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initial begin
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trk_name = $sformatf("%m.out");
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trk_h = $fopen(trk_name, "w");
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$fdisplay(trk_h, "Tracker: %s", trk_name);
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$display("Starting tracker: %s", trk_name);
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$fmonitor(trk_h, "@%6t: %b %b %h %h", $time,
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intf.rst_n, intf.clk, intf.data_in, intf.data_out);
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end
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function void be_done();
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$display("Closing tracker %s", trk_name);
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$fclose(trk_h);
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endfunction
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endmodule
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